Patents by Inventor Pramod BHARDWAJ

Pramod BHARDWAJ has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240111693
    Abstract: Techniques to provide transaction redundancy in an IC include receiving an original memory access request directed to a first memory aperture, constructing a redundant memory access directed to a second memory aperture, and selectively returning a response of the first or second memory aperture to an originator based on contents of the responses. For a write operation, if acknowledgement indicators of the responses indicate success, a response is returned to the originator. For a read operation, if acknowledgement indicators of the responses indicate success and data returned in the response match one another, a response is returned to the originator. If the acknowledgement indicators indicate success, but the data does not match, a retry of the original and redundant read requests is initiated. If any of the acknowledgement indicators do not indicate success, an error is declared. In a mixed-criticality embodiment, the redundant memory access request may be constructed selectively.
    Type: Application
    Filed: September 30, 2022
    Publication date: April 4, 2024
    Inventors: Krishnan SRINIVASAN, Ygal ARBEL, Sagheer AHMAD, Sarosh I. AZAD, Pramod BHARDWAJ, Yanran CHEN, James MURRAY
  • Publication number: 20230290189
    Abstract: Embodiments herein describe wrapping non-safety compliant hardware resources with error detection checking to satisfy a safety standard. Doing so permits non-safety compliant hardware to be used to perform one or more tasks in a system that, as a whole, satisfies a particular safety standard (e.g., one of the ASIL QM, A, B, C, and D grades).
    Type: Application
    Filed: March 10, 2022
    Publication date: September 14, 2023
    Inventors: Yanran CHEN, Sagheer AHMAD, Amitava MAJUMDAR, Pramod BHARDWAJ
  • Publication number: 20230085149
    Abstract: In one example, an integrated circuit (IC) is provided that includes data circuitry and a processing circuitry. The data circuitry is configured to provide data to be transferred to a different circuitry within the IC or to an external IC. The processing circuitry is configured to: read the data provided by the data circuitry before it is transferred to the different circuitry or the external IC; calculate a first signature for the data; attach the first signature to the data; calculate, after transferring the data to the different circuitry or the external IC, a second signature for the data; extract the first signature corresponding to the data; compare the first signature to the second signature; and generate a signal based on a comparison of the first signature to the second signature.
    Type: Application
    Filed: September 16, 2021
    Publication date: March 16, 2023
    Inventors: Pramod BHARDWAJ, Sarosh I. AZAD, Wern-Yan KOE, Amitava MAJUMDAR