Abstract: CMOS devices on SOI and a method for making such devices with ultra-thin Si channel regions and thick Si drain and source regions for good contact surfaces are described.

Abstract: A method of fabricating a semiconductor integrated circuit by providing a semiconductor body having a major surface; depositing a first layer of a conductive material on the major surface of the semiconductor body, and depositing a layer of a refractory silicide on the first layer of conductive material. Portions of said refractory silicide layer are marked to define a first pattern thereon; and the silicide layer is etched down to the first conductive layer in order to produce the pattern defined by the masking step. Portions of the body are masked again to define a second pattern thereon; etching said first conductive layer in said second masking pattern. The semiconductor body is sintered to stabilize the contact between first conductive layer and layer of refractory silicide. A layer of dielectric material is deposited on body. Portions of said dielectric material are masked to define a third pattern thereon; and the dielectric material is etched to silicide layer in accordance with the third pattern.