Patents by Inventor Pramod Malatkar
Pramod Malatkar has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 11327050Abstract: Disclosed herein are systems and methods for mechanical failure monitoring, detection, and classification in electronic assemblies. In some embodiments, a mechanical monitoring apparatus may include: a fixture to receive an electronic assembly; an acoustic sensor; and a computing device communicatively coupled to the acoustic sensor, wherein the acoustic sensor is to detect an acoustic emission waveform generated by a mechanical failure of the electronic assembly during testing.Type: GrantFiled: February 20, 2018Date of Patent: May 10, 2022Assignee: Intel CorporationInventors: Kyle Yazzie, Rajesh Kumar Neerukatti, Naga Sivakumar Yagnamurthy, David C. McCoy, Pramod Malatkar, Frank P. Prieto
-
Patent number: 11322456Abstract: A foundation layer having a stiffener and methods of forming a stiffener are described. One or more dies are formed over the foundation layer. Each die has a front side surface that is electrically coupled to the foundation layer and a back side surface that is opposite from the front side surface. A stiffening layer (or a stiffener) is formed on the back side surface of at least one of the dies. The stiffening layer may be directly coupled to the back side surface of the one or more dies without an adhesive layer. The stiffening layer may include one or more materials, including at least one of a metal, a metal alloy, and a ceramic. The stiffening layer may be formed to reduce warpage based on the foundation layer and the dies. The one or more materials of the stiffening layer can be formed using a cold spray.Type: GrantFiled: June 30, 2017Date of Patent: May 3, 2022Assignee: Intel CorporationInventors: Feras Eid, Venkata Suresh R. Guthikonda, Shankar Devasenathipathy, Chandra M. Jha, Je-Young Chang, Kyle Yazzie, Prasanna Raghavan, Pramod Malatkar
-
Publication number: 20220068861Abstract: A packaged semiconductor die with a bumpless die-package interface and methods of fabrication are described. For example, a semiconductor package includes a substrate having a land side with a lowermost layer of conductive vias. A semiconductor die is embedded in the substrate and has an uppermost layer of conductive lines, one of which is coupled directly to a conductive via of the lowermost layer of conductive vias of the substrate. In another example, a semiconductor package includes a substrate having a land side with a lowermost layer of conductive vias. A semiconductor die is embedded in the substrate and has an uppermost layer of conductive lines with a layer of conductive vias disposed thereon. At least one of the conductive lines is coupled directly to a conductive via of the semiconductor die which is coupled directly to a conductive via of the lowermost layer of conductive vias of the substrate.Type: ApplicationFiled: November 10, 2021Publication date: March 3, 2022Inventors: Pramod MALATKAR, Weng Hong TEH, John S. GUZEK, Robert L. SANKMAN
-
Patent number: 11201128Abstract: A packaged semiconductor die with a bumpless die-package interface and methods of fabrication are described. For example, a semiconductor package includes a substrate having a land side with a lowermost layer of conductive vias. A semiconductor die is embedded in the substrate and has an uppermost layer of conductive lines, one of which is coupled directly to a conductive via of the lowermost layer of conductive vias of the substrate. In another example, a semiconductor package includes a substrate having a land side with a lowermost layer of conductive vias. A semiconductor die is embedded in the substrate and has an uppermost layer of conductive lines with a layer of conductive vias disposed thereon. At least one of the conductive lines is coupled directly to a conductive via of the semiconductor die which is coupled directly to a conductive via of the lowermost layer of conductive vias of the substrate.Type: GrantFiled: December 23, 2015Date of Patent: December 14, 2021Assignee: Intel CorporationInventors: Pramod Malatkar, Weng Hong Teh, John S. Guzek, Robert L. Sankman
-
Publication number: 20210242105Abstract: Techniques and mechanisms for promoting heat conduction in a packaged device using a heat spreader that is fabricated by a build-up process. In an embodiment, 3D printing of a heat spreader successively deposit layers of a thermal conductor material, where said layers variously extend each over a respective one or more IC dies. The heat spreader forms a flat top side, wherein a bottom side of the heat spreader extends over, and conforms at least partially to, different respective heights of various IC dies. In another embodiment, fabrication of a portion of the heat spreader comprises printing pore structures that contribute to a relatively low thermal conductivity of said portion. An average orientation of the oblong pores contributes to different respective thermal conduction properties for various directions of heat flow.Type: ApplicationFiled: February 4, 2020Publication date: August 5, 2021Applicant: INTEL CORPORATIONInventors: Jesus Gerardo Reyes Schuldes, Shankar Devasenathipathy, Pramod Malatkar, Aravindha Antoniswamy, Kyle Arrington
-
Patent number: 10985080Abstract: An electronic package that includes a substrate and an electronic component attached to the substrate. A laminated layer is attached to an upper surface of the substrate such that the laminated layer covers the electronic component. The electronic package may further include a stiffener mounted on the laminated layer where the stiffener is over the electronic component.Type: GrantFiled: November 24, 2015Date of Patent: April 20, 2021Assignee: Intel CorporationInventors: Pramod Malatkar, Kyle Yazzie, Naga Sivakumar Yagnamurthy, Richard J. Harries, Dilan Seneviratne, Praneeth Akkinepally, Xuefei Wan, Yonggang Li, Robert L. Sankman
-
Patent number: 10957656Abstract: Disclosed herein are integrated circuit (IC) packages with an electronic component having a patterned protective material on a face, as well as related devices and methods. In some embodiments, a computing device may include: an integrated circuit (IC) package with an electronic component having a protective material on the back face of the electronic component, where the protective material is patterned to include an area on the back face of the electronic component that is not covered by the protective material; a circuit board, where the IC package is electrically coupled to the circuit board; and a heat spreader, where the heat spreader is secured to the circuit board and in thermal contact with the area on the back face of the electronic component that is not covered by the protective material.Type: GrantFiled: September 27, 2017Date of Patent: March 23, 2021Assignee: Intel CorporationInventors: Kyle Yazzie, Naga Sivakumar Yagnamurthy, Pramod Malatkar, Chia-Pin Chiu, Mohit Mamodia, Mark J. Gallina, Rajesh Kumar Neerukatti, Joseph Bautista, Michael Gregory Drake
-
Publication number: 20210082798Abstract: Embodiments disclosed herein include electronic packages. In an embodiment, the electronic package comprises a first substrate; a second substrate; and an array of interconnects electrically coupling the first substrate to the second substrate. In an embodiment, the array of interconnects comprises first interconnects, wherein the first interconnects have a first volume and a first material composition, and second interconnects, wherein the second interconnects have a second volume and a second material composition, and wherein the first volume is different than the second volume and/or the first material composition is different than the second material composition.Type: ApplicationFiled: September 18, 2019Publication date: March 18, 2021Inventors: Xiao LU, Jiongxin LU, Christopher COMBS, Alexander HUETTIS, John HARPER, Jieping ZHANG, Nachiket R. RARAVIKAR, Pramod MALATKAR, Steven A. KLEIN, Carl DEPPISCH, Mohit SOOD
-
Publication number: 20200357752Abstract: Disclosed herein are integrated circuit (IC) packages with an electronic component having a patterned protective material on a face, as well as related devices and methods. In some embodiments, a computing device may include: an integrated circuit (IC) package with an electronic component having a protective material on the back face of the electronic component, where the protective material is patterned to include an area on the back face of the electronic component that is not covered by the protective material; a circuit board, where the IC package is electrically coupled to the circuit board; and a heat spreader, where the heat spreader is secured to the circuit board and in thermal contact with the area on the back face of the electronic component that is not covered by the protective material.Type: ApplicationFiled: September 27, 2017Publication date: November 12, 2020Applicant: Intel CorporationInventors: Kyle Yazzie, Naga Sivakumar Yagnamurthy, Pramod Malatkar, Chia-Pin Chiu, Mohit Mamodia, Mark J. Gallina, Rajesh Kumar Neerukatti, Joseph Bautista, Michael Gregory Drake
-
Patent number: 10634594Abstract: A membrane test for mechanical testing of wearable devices is described. A mechanical testing system includes an actuation mechanism including a clamp to hold a membrane including stretchable electronics over an opening in the actuation mechanism, wherein the actuation mechanism is to apply pressure to the membrane through the opening; and a testing logic to control the application and release of pressure on the membrane by the actuation mechanism.Type: GrantFiled: March 18, 2016Date of Patent: April 28, 2020Assignee: Intel CorporationInventors: Ravindranth V. Mahajan, Rajendra C. Dias, Pramod Malatkar, Steven A. Klein, Vijay Subramania, Aleksandar Aleksov, Robert L. Sankman
-
Patent number: 10607909Abstract: In accordance with disclosed embodiments, there are provided methods, systems, and apparatuses for implementing a thermal solution for 3D packaging.Type: GrantFiled: April 2, 2016Date of Patent: March 31, 2020Assignee: Intel CorporationInventors: Purushotham Kaushik Muthur Srinath, Pramod Malatkar, Sairam Agraharam, Chandra M. Jha, Arnab Choudhury, Nachiket R. Raravikar
-
Publication number: 20200066655Abstract: A foundation layer having a stiffener and methods of forming a stiffener are described. One or more dies are formed over the foundation layer. Each die has a front side surface that is electrically coupled to the foundation layer and a back side surface that is opposite from the front side surface. A stiffening layer (or a stiffener) is formed on the back side surface of at least one of the dies. The stiffening layer may be directly coupled to the back side surface of the one or more dies without an adhesive layer. The stiffening layer may include one or more materials, including at least one of a metal, a metal alloy, and a ceramic. The stiffening layer may be formed to reduce warpage based on the foundation layer and the dies. The one or more materials of the stiffening layer can be formed using a cold spray.Type: ApplicationFiled: June 30, 2017Publication date: February 27, 2020Inventors: Feras EID, Venkata Suresh R. GUTHIKONDA, Shankar DEVASENATHIPATHY, Chandra M. JHA, Je-Young CHANG, Kyle YAZZIE, Prasanna RAGHAVAN, Pramod MALATKAR
-
Patent number: 10499461Abstract: A thermal heat for integrated circuit die processing is described that includes a thermal barrier. In one example, the thermal head has a ceramic heater configured to carry an integrated circuit die, a metal base, and a thermal barrier between the heater and the base.Type: GrantFiled: December 21, 2015Date of Patent: December 3, 2019Assignee: Intel CorporationInventors: Mohit Mamodia, Kyle Yazzie, Dingying Xu, Kuang Liu, Paul J. Diglio, Pramod Malatkar
-
Patent number: 10475750Abstract: In accordance with disclosed embodiments, there are provided methods, systems, and apparatuses for implementing an organic stiffener with an EMI shield for RF integration. For instance, in accordance with one embodiment, there is an apparatus having therein: a substrate layer having electrical traces and a ground plane therein; a functional semiconductor die electrically interfaced to the electrical traces of the substrate layer; a heat pipe thermally interfaced to a top surface of the functional semiconductor die; one or more interposers of an organic dielectric material electrically connected to the ground plane of the substrate layer and electrically connected to the heat pipe; in which the one or more interposers form the electromagnetic shield to electrically shield the functional semiconductor die; and further in which the one or more interposers form the organic stiffener are to mechanically retain the substrate layer in a planer form. Other related embodiments are disclosed.Type: GrantFiled: April 2, 2016Date of Patent: November 12, 2019Assignee: Intel CorporationInventors: Vijay K. Nair, Pramod Malatkar
-
Publication number: 20190304931Abstract: Electronic device shape configuration technology is disclosed. In an example, an electronic device substrate is provided that can comprise a top surface, and a bottom surface opposing the top surface. The top surface and/or the bottom surface can have a non-rectangular shaped perimeter. An electronic device die is also provided that can comprise a top surface, and a bottom surface opposing the top surface. The top surface and/or the bottom surface can have a non-rectangular shaped perimeter. In addition, an electronic device package is provided that can comprise a substrate having a top surface configured to receive a die and a bottom surface opposing the top surface. The package can also include a die having a top surface and a bottom surface opposing the top surface. The die can be coupled to the top surface of the substrate. The top surface and/or the bottom surface of either the substrate, or the die, or both can have a non-rectangular shaped perimeter.Type: ApplicationFiled: October 2, 2018Publication date: October 3, 2019Applicant: Intel CorporationInventors: Pramod Malatkar, Sairam Agraharam, Shawna Liff
-
Publication number: 20190257793Abstract: Disclosed herein are systems and methods for mechanical failure monitoring, detection, and classification in electronic assemblies. In some embodiments, a mechanical monitoring apparatus may include: a fixture to receive an electronic assembly; an acoustic sensor; and a computing device communicatively coupled to the acoustic sensor, wherein the acoustic sensor is to detect an acoustic emission waveform generated by a mechanical failure of the electronic assembly during testing.Type: ApplicationFiled: February 20, 2018Publication date: August 22, 2019Applicant: Intel CorporationInventors: Kyle Yazzie, Rajesh Kumar Neerukatti, Naga Sivakumar Yagnamurthy, David C. McCoy, Pramod Malatkar, Frank P. Prieto
-
Patent number: 10290569Abstract: An apparatus, comprising a first platform comprising a first working surface having a first non-planar portion; and a second platform comprising a second working surface having a second non-planar portion, wherein: the second working surface is opposite the first working surface, a distance between the first working surface and the second working surface is adjustable, the first non-planar portion comprises a first curved portion, and the second non-planar portion comprises a second curved portion opposite the first curved portion.Type: GrantFiled: September 29, 2017Date of Patent: May 14, 2019Assignee: Intel CorporationInventors: Kyle Yazzie, Venkata Suresh R. Guthikonda, Patrick Nardi, Santosh Sankarasubramanian, Kevin Y. Lin, Leigh M. Tribolet, John L. Harper, Pramod Malatkar
-
Patent number: 10278318Abstract: A method of assembly comprising providing an assembly probe, the assembly probe having an end coupling face; providing a droplet of fluid on the end coupling face of the assembly probe; coupling an electronic component to the end coupling face of the assembly probe with the fluid droplet, the electronic component having a peripheral dimension equal to or less than 2 mm in each of length, width and height; placing the electronic component on a substrate with the assembly probe; decoupling the electronic component from the end coupling face of the assembly probe; and assembling the electronic component to the substrate.Type: GrantFiled: December 18, 2015Date of Patent: April 30, 2019Assignee: Intel CorporationInventors: Kyle Yazzie, Pramod Malatkar, Xiao Lu, Daniel Chavez-Clemente
-
Publication number: 20190103345Abstract: An apparatus, comprising a first platform comprising a first working surface having a first non-planar portion; and a second platform comprising a second working surface having a second non-planar portion, wherein: the second working surface is opposite the first working surface, a distance between the first working surface and the second working surface is adjustable, the first non-planar portion comprises a first curved portion, and the second non-planar portion comprises a second curved portion opposite the first curved portion.Type: ApplicationFiled: September 29, 2017Publication date: April 4, 2019Inventors: Kyle YAZZIE, Venkata Suresh R. GUTHIKONDA, Patrick NARDI, Santosh SANKARASUBRAMANIAN, Kevin Y. LIN, Leigh M. TRIBOLET, John L. HARPER, Pramod MALATKAR
-
Patent number: 10231338Abstract: Methods of forming a package structures comprising a trench are described. An embodiment includes a first die disposed on a first substrate, and at least one interconnect structure disposed on a peripheral region of the first substrate. A molding compound is disposed on a portion of the first substrate and on the first die, wherein a trench opening is disposed in the molding compound that is located between the at least one interconnect structure and the first die.Type: GrantFiled: June 24, 2015Date of Patent: March 12, 2019Assignee: INTEL CORPORATIONInventors: Naga Sivakumar Yagnamurthy, Huiyang Fei, Pramod Malatkar, Prasanna Raghavan, Robert Nickerson