Abstract: A multiported LAN switch comprised of legacy local area network ports and ATM ports. Each ATM port comprising a hardware forwarding engine for bridging LAN frames from the LAN ports to the ATM port. The hardware forwarding engine converts layer 2 protocols between the dissimilar ports expediently, without requiring intervention by a microprocessor. A substantial performance gain is attained compared to microprocessor controlled format converters. Both LAN emulation and virtual LANs are supported.

Abstract: A multiported LAN switch comprised of legacy local area network ports and ATM ports. Each ATM port comprising a hardware forwarding engine for bridging LAN frames from the LAN ports to the ATM port. The hardware forwarding engine converts layer 2 protocols between the dissimilar ports expediently, without requiring intervention by a microprocessor. A substantial performance gain is attained compared to microprocessor controlled format converters. Both LAN emulation and virtual LANs are supported.

Abstract: A multiported LAN switch comprised of legacy local area network ports and ATM ports. Each ATM port comprising a hardware forwarding engine for bridging LAN frames from the LAN ports to the ATM port. The hardware forwarding engine converts layer 2 protocols between the dissimilar ports expediently, without requiring intervention by a microprocessor. A substantial performance gain is attained compared to microprocessor controlled format converters. Both LAN emulation and virtual LANs are supported.

Abstract: A multiported LAN switch comprised of legacy local area network ports and ATM ports. Each ATM port comprising a hardware forwarding engine for bridging LAN frames from the LAN ports to the ATM port. The hardware forwarding engine converts layer 2 protocols between the dissimilar ports expediently, without requiring intervention by a microprocessor. A substantial performance gain is attained compared to microprocessor controlled format converters. Both LAN emulation and virtual LANs are supported.

Abstract: A multiported LAN switch comprised of legacy local area network ports and ATM ports. Each ATM port comprising a hardware forwarding engine for bridging LAN frames from the LAN ports to the ATM port. The hardware forwarding engine converts layer 2 protocols between the dissimilar ports expediently, without requiring intervention by a microprocessor. A substantial performance gain is attained compared to microprocessor controlled format converters. Both LAN emulation and virtual LANs are supported.

Abstract: Mechanism for use in an internetworking device incorporating a translational bridging function to provide load balancing across multiple instances of the same destination address. Traffic originating with clients in the transparently bridged domain is distributed over multiple communication paths to the multiple instances of the destination address in the source route bridging domain. The internetworking device sends an explorer frame over each interface in the source route bridging domain to discover all parallel paths to the destination address. The internetworking device receives a response from each instance of the destination address over all possible paths. The routing information contained in the responses is used to create entries in a cache in the internetworking device. Load balancing is performed by using the source address of the transparently bridged clients as a key to select a specific path for each such client.

Abstract: A multiported LAN switch comprised of legacy local area network ports and ATM ports. Each ATM port comprising a hardware forwarding engine for bridging LAN frames from the LAN ports to the ATM port. The hardware forwarding engine converts layer 2 protocols between the dissimilar ports expediently, without requiring intervention by a microprocessor. A substantial performance gain is attained compared to microprocessor controlled format converters. Both LAN emulation and virtual LANs are supported.

Abstract: A memory interface for multi-port access to a memory unit, such as a static random-access memory (SRAM) device. The memory interface, which is generally adapted for a local area network (LAN) forwarding engine, provides single port read/write access to SRAM device, and arbitrates requests from the access interfaces to allocate bandwidth of the SRAM device among the requests. One embodiment allocates at least 50% of the bandwidth to a peripheral component interface (PCI) bus target interface and a PCI bus master interface, collectively. The arbitration logic may include a plurality of bandwidth control registers associated with respective access interfaces used to determine a permitted amount of bandwidth that an access interface is to have, wherein a request from an access interface is masked based on a value in its associated bandwidth control register. Arbitration can further allocate bandwidth using time division multiplexing.