Patents by Inventor Pramod Pandey

Pramod Pandey has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220155009
    Abstract: Aspects of the present disclosure include methods of producing solid dry manure. In certain embodiments, the methods comprise disposing solid manure on a first conveyor operably coupled to a microwave radiation source. Such methods further comprise, using the first conveyor, conveying the solid manure past the microwave radiation source, and during the conveying, exposing the solid manure to microwave radiation emitted from the microwave radiation source to produce solid dry manure. Also provided are apparatuses that find use, e.g., in practicing the methods of the present disclosure.
    Type: Application
    Filed: April 1, 2020
    Publication date: May 19, 2022
    Inventor: Pramod Pandey
  • Patent number: 8578458
    Abstract: In at least one implementation a method includes receiving an identifier associated with a device, entering the identifier into a network controller device, inviting the device associated with the identifier to join a network, admitting the device associated with the identifier to the network, sending the device associated with the identifier a name of the network, and confirming that the device has joined the network as a device recognized by the network controller device.
    Type: Grant
    Filed: March 3, 2011
    Date of Patent: November 5, 2013
    Assignee: Lantiq Deutschland GmbH
    Inventors: Vladimir Oksman, Pramod Pandey, Joon Bae Kim
  • Publication number: 20120246331
    Abstract: A Home Network and Multimode Modem are provided for coupling devices of different standards/protocols for transmitting/receiving data over the Home Network. The modem is configured to transmit/receive data in both a first mode and a second mode. The first mode provides a first standard/protocol for Home Networking for transmitting and/or receiving data between devices of the Home Network and the second mode provides a second standard/protocol for Home Networking for transmitting/receiving data between devices of the Home Network. A controller dynamically switches the modem between the first and second modes.
    Type: Application
    Filed: January 5, 2011
    Publication date: September 27, 2012
    Inventors: Peter Heller, Pramod Pandey, Richard Gross
  • Publication number: 20120226901
    Abstract: Secure message transfer is provided in a network including at least a Home Area Network (HAN) having network devices A, B and C. The Home Area Network is capable to connect domains having different transmission formats and includes a secure communication protocol. Device A is capable to communicate at least one message to the device C according to the secure communication protocol, and device B is capable to receive at least one message from device A sent for reception and decryption by device C. A device D controls the secure message transfer and selectively disables device B from decrypting the message received by device B that is sent from device A to device C for decryption.
    Type: Application
    Filed: September 2, 2011
    Publication date: September 6, 2012
    Applicant: LANTIQ DEUTSCHLAND GMBH
    Inventors: Pramod Pandey, Joshua Grossman, Daniel Scharfen
  • Publication number: 20110271333
    Abstract: In at least one implementation a method includes receiving an identifier associated with a device, entering the identifier into a network controller device, inviting the device associated with the identifier to join a network, admitting the device associated with the identifier to the network, sending the device associated with the identifier a name of the network, and confirming that the device has joined the network as a device recognized by the network controller device.
    Type: Application
    Filed: March 3, 2011
    Publication date: November 3, 2011
    Inventors: Vladimir Oksman, Pramod Pandey, Joon Bae Kim
  • Patent number: 7676631
    Abstract: A CPU 3 having a processor 1 and an internal data cache 7 IS operated in combination with a dummy interface 13 which simulates the existence of an external memory 17 having the same address space as the cache memory 7 but which does not store data written to it. In this way, a conventional CPU can be operated without read/write access to an external memory in respect of at least part of its memory address space, and therefore with a higher performance resulting from faster memory access and reduced external memory requirements. The CPU 3 may be one of a set of CPU chips 20, 21 in a data processing system, one or more of those chips 20 optionally having read/write access to an external memory 23.
    Type: Grant
    Filed: August 5, 2002
    Date of Patent: March 9, 2010
    Assignee: Infineon Technologies AG
    Inventors: Taro Kamiko, Pramod Pandey
  • Patent number: 7217794
    Abstract: The present invention provides compounds that inhibit Factor XIa and methods of preventing or treating undesired thrombosis by administering a compound of the invention to a mammal. The invention also provides three-dimensional structures of Factor XIa and methods for designing or selecting additional Factor XIa inhibitors using these structures.
    Type: Grant
    Filed: April 2, 2004
    Date of Patent: May 15, 2007
    Assignee: Daiamed, Inc.
    Inventors: Sherin S. Abdel-Meguid, Robert E. Babine, Hongfeng Deng, Lei Jin, Jian Lin, Scott R. Magee, Harold V. Meyers, Pramod Pandey, Michael J. Rynkiewicz, David T. Weaver, Zihong Gho, Thomas D. Bannister
  • Publication number: 20070065557
    Abstract: The present invention relates to non sweet food binder composition. Particularly, the food binder composition can be used in the preparation of savory snack bars, savory nutritional bars, or in savory food products used as snack or meal replacement, containing varied levels of protein, fiber, minerals, vitamins and other bioactive substances or nutritional supplements.
    Type: Application
    Filed: September 19, 2006
    Publication date: March 22, 2007
    Inventors: Pramod Pandey, Julia Guerrero, Margaret Ciaston
  • Publication number: 20070026129
    Abstract: The present invention relates to an aerated food composition and a process of making such composition. Particularly, the invention relates to an aerated food composition having a high protein content as well as pleasant organoleptic properties.
    Type: Application
    Filed: July 19, 2006
    Publication date: February 1, 2007
    Inventors: Pramod Pandey, Julia Guerrero, Margaret Ciaston
  • Publication number: 20060164988
    Abstract: A Ethernet switch 1 includes a monitoring unit 9 for policing the amount of traffic on each of a plurality of flows or groups of flows. The monitoring unit has a memory, implemented in hardware as a RAM memory, having a section of each of the flows or groups of flows, and acting as a token bucket for those flows or group of flows.
    Type: Application
    Filed: September 6, 2002
    Publication date: July 27, 2006
    Inventors: Shridhar Mishra, Pramod Pandey, Guruprasad Ardhanari
  • Publication number: 20050265358
    Abstract: A plurality of data switches such as Ethernet switches 1, 2, 3, 5 are connected to each other using their ports for receiving and transmitting packets. A given one of the switches 5 operates as a master switch, which transmits instructions to the other switches 1, 2, 3 as command packets, and receives responses back from them as response packets. The slave switches 1, 2, 3 are connected pairwise. The command packets pass through the network until they reach a slave switch 1, 2, 3 to implement them, and the response 10 packets pass through the network to the master switch 5.
    Type: Application
    Filed: September 6, 2002
    Publication date: December 1, 2005
    Inventors: Shridhar Mishra, Pramod Pandey
  • Publication number: 20050235111
    Abstract: A CPU 3 having a processor 1 and an internal data cache 7 IS operated in combination with a dummy interface 13 which simulates the existence of an external memory 17 having the same address space as the cache memory 7 but which does not store data written to it. In this way, a conventional CPU can be operated without read/write access to an external memory in respect of at least part of its memory address space, and therefore with a higher performance resulting from faster memory access and reduced external memory requirements. The CPU 3 may be one of a set of CPU chips 20, 21 in a data processing system, one or more of those chips 20 optionally having read/write access to an external memory 23.
    Type: Application
    Filed: August 5, 2002
    Publication date: October 20, 2005
    Inventors: Taro Kamiko, Pramod Pandey
  • Patent number: 6934205
    Abstract: A processor assisted memory BIST to identify detective memory addresses. The processor generates the address to be tested and the BIST generates the test data used to test the memory. Data is written to an read from memory. The read data is compared with the test data. If a mismatch occurs, the BIST generates an interrupt to identify the processor. Since the processor generated the address, the defective memory address is identified. The defective memory address can subsequently be replaced with redundant memory cells.
    Type: Grant
    Filed: September 6, 2000
    Date of Patent: August 23, 2005
    Assignee: Infineon Technologies Aktiengesellschaft
    Inventors: Pramod Pandey, Ali Najafi
  • Publication number: 20050143317
    Abstract: The present invention provides compounds that inhibit Factor XIa and methods of preventing or treating undesired thrombosis by administering a compound of the invention to a mammal. The invention also provides three-dimensional structures of Factor XIa and methods for designing or selecting additional Factor XIa inhibitors using these structures.
    Type: Application
    Filed: April 2, 2004
    Publication date: June 30, 2005
    Inventors: Sherin Abdel-Meguid, Robert Babine, Hongfeng Deng, Lei Jin, Jian Lin, Scott Magee, Harold Meyers, Pramod Pandey, Michael Rynkiewicz, David Weaver, Zihong Gho, Thomas Bannister
  • Publication number: 20030168662
    Abstract: An IC with improved reference clock distribution is provided, comprising a reference oscillator (2) and several subcircuits (4 to 7), each connected via a clock input terminal (41, 51, 61, 71) and a clock tree (8) with the oscillator (2). Via that clock tree (8), a harmonic clock signal is distributed, which is shaped into a square wave within the subcircuits. The IC described features significantly less signal distortions and requires no introduction of additional delay elements at the top level clock tree (8).
    Type: Application
    Filed: March 8, 2002
    Publication date: September 11, 2003
    Inventor: Pramod Pandey