Abstract: A touch sensing system comprises a signal generator (Tx), which is configured to provide an AC signal, a signal receiver (Rx), which is configured to perform a signal detection, a first transmitter node (T1), which is connected to the signal generator (Tx) in a switchable fashion, a second transmitter node (T2), which is connected to the first transmitter node (T1) in a switchable fashion and to a reference potential terminal (GND) in a switchable fashion, a first receiver node (R1), which is connected to the signal receiver (Rx) in a switchable fashion and to the first transmitter node (T1) in a switchable fashion, a second receiver node (R2), which is connected to the first receiver node (R1) in a switchable fashion and to the reference potential terminal (GND) in a switchable fashion, a first electrode (E1), which is connected to the second transmitter node (T2) in a switchable fashion, a second electrode (E2), which is connected to the second receiver node (R2) in a switchable fashion, and a capacitance m

Abstract: A multi-current-source comprises a voltage converter (VC), a first current source (CS1) with a first terminal (A1) which is adapted to be coupled to an output (OUT) of a voltage converter (VC) and with a second terminal (B1) which is adapted to be coupled to an input (IN) of the voltage converter (VC), at least a second current source (CS2) with a first terminal (A2) which is adapted to be coupled to the output (OUT) of the voltage converter (VC) and with a second terminal (B2) which is adapted to be coupled to the input (IN) of the voltage converter (VC), wherein the first current source (CS1) being adapted to provide a first load current (Il1) at its first terminal (A1) the first load current (Il1) being regulated to a first constant value and to provide a first unidirectional error current (Ierr1) at its second terminal (B1), wherein the at least one second current source (CS2) being adapted to provide a second load current (Il2) at its first terminal (A2), the second load current (Il2) being regulated to

Abstract: A DC/DC converter arrangement includes an input terminal to receive a supply voltage, an output terminal to provide an output voltage and a switching arrangement, including a coil and at least two switches to provide a Buck-Boost conversion. The arrangement further includes a current detection circuit which is coupled to the switching arrangement for sensing a coil current and a comparator, including a first input which is coupled to the output terminal and a second input which is coupled to an output of the current detection circuit. An output of the comparator is coupled to the switching arrangement. Furthermore, the arrangement includes a ramp generator which is coupled to the first or the second input of the comparator.

Abstract: A band gap reference circuit comprises a first branch (1) having a first transistor (Q1) and a first temperature-dependent resistive element (S0). A second branch of the band gap reference comprises a second transistor (Q2) having a different size compared to the first transistor (Q1). An output branch (3) comprises a second temperature-dependent resistive element (S1, S2), that second temperature-dependent resistive element being coupled to an output terminal (Vref). At least one of the first and second temperature-dependent resistive elements (S0, S1, S2) comprises a transistor (M2) being arranged in a current path of the respective branch (1, 3) and being controlled such that it operates in a linear region of its characteristics.

Abstract: A touch sensing system comprises a signal generator (Tx), which is configured to provide an AC signal, a signal receiver (Rx), which is configured to perform a signal detection, a first transmitter node (T1), which is connected to the signal generator (Tx) in a switchable fashion, a second transmitter node (T2), which is connected to the first transmitter node (T1) in a switchable fashion and to a reference potential terminal (GND) in a switchable fashion, a first receiver node (R1), which is connected to the signal receiver (Rx) in a switchable fashion and to the first transmitter node (T1) in a switchable fashion, a second receiver node (R2), which is connected to the first receiver node (R1) in a switchable fashion and to the reference potential terminal (GND) in a switchable fashion, a first electrode (E1), which is connected to the second transmitter node (T2) in a switchable fashion, a second electrode (E2), which is connected to the second receiver node (R2) in a switchable fashion, and a capacitance m

Abstract: A voltage converter (10) comprises an input (11) for receiving an input voltage (VIN), a first output (12) for providing a first output voltage (VPOS) and a second output (13) for providing a second output voltage (VNEG). The first output voltage (VPOS) and the second output voltage (VNEG) have opposite polarities. A switching arrangement (14) of the voltage converter (10) is designed to provide energy to an inductor (15) in a charging phase (A) of operation and to provide energy from the inductor (15) to the first output (12) and, via a flying capacitor (16), to the second output (13) in a discharging phase of operation. The first duration (t1) of the charging phase (A) of operation is controlled such that the difference between a first predetermined value and the sum of the absolute value of the first output voltage (VPOS) and of the second output voltage (VNEG) is minimized.

Abstract: A controlled current source comprises a signal input to receive a control input bus signal (D0, . . . , D[n?1]), a mapping unit (MU) with an input coupled to the signal input and an output to provide an internal control bus signal (d0, . . . , dn, Hc), a reference generator (RG) with an input coupled to the output of the mapping unit (MU) and with a low reference output to provide a low reference potential (Vgl) and with a high reference output to provide a high reference potential (Vgh), a current generating unit (CG) with a first input coupled to the output of the mapping unit (MU), a second input coupled to the output of the reference generator (RG) and an output to provide an output current (Iout) controlled by the control input bus signal (D0, . . . , D[n?1]) and the low and high reference potentials (Vgh, Vgl). Furthermore, a method for sourcing a current is provided.

Abstract: A current source regulator for controlling an output device (Mp) of current source, the output device (Mp) providing an output current (Isrc) to a load. The current source regulator comprises a first feedback loop (1) and second feedback loop (2). The first feedback loop (1) includes a first sensing path to provide a first sensing signal (Is1) for comparison with a first reference to generate a first control signal. The second feedback loop (2) comprises a second sensing path to provide a second sensing signal (Is3, Is3?) for comparison with a second reference (Ib5) to generate a charging current signal (Icharge). The charging current signal (Icharge) is applied to the control signal during a transient state of the current source regulator.

Abstract: A controlled charge pump comprises a clock operated charge pump having an output terminal to provide an output voltage. A first sub-circuit is coupled to the output terminal of the clocked operated charge pump and adapted to provide a first control signal in response to a comparison of the output voltage with a first reference signal. A second sub-circuit is coupled to the clocked operated charge pump and provides a second control signal in response to a comparison of a switch current within the clocked operated charge pump with a second reference signal. A clock skip controller is adapted to control the mode of operation of the clocked operated charge pump in response to that first and second control signals.

Abstract: A power source arrangement comprises a controlled and clocked operated power source, that power source providing an output voltage out of a plurality of output voltages in response to a first multiplication factor. One or more regulated current sources are connected to the controlled and clocked operated power source to provide an output current to respective loads. Each of the one or more regulated current sources is adapted to provide a first indication signal upon a regulated operation of the respective current source. The power source arrangement further comprises a dummy power source as well as a dummy current source connected to the dummy power source. The dummy current source receives a load signal corresponding to a voltage drop over the loads connected to the one or more regulated current sources and provides a second indication signal in response thereto.

Abstract: A filtering arrangement comprises a reference voltage input (1) and a compensation current arrangement (10) coupled to the reference voltage input (1) and configured to provide a control current at a current output (2) as a function of a voltage at the reference voltage input (1). The filtering arrangement also comprises a first and a second current source (20, 30) each having a control input (4, 5) coupled to the current output (2), a first and a second filter input (7, 8), and a first transistor (T1) and a second transistor (T2). The first transistor (T1) has a first connection (T11), a second connection (T12) and a control connection (T1c), where its first connection (T11) is coupled to the first current source (20) and its second connection (T12) is coupled to the first filter input (7) through a first resistor (R1).

Abstract: A method for DC/DC conversion which comprises the steps of controlling a first switch (10) for coupling a supply terminal (5) to a first terminal (60) of an inductor (2) and a second switch (20) for coupling the first terminal (60) to a ground potential terminal (8). The method further comprises controlling a third switch (30) for coupling a second terminal (61) of the inductor (2) to the ground potential terminal (8) and a fourth switch (40) for coupling the second terminal (61) to an output terminal (6). A control sequence is used to control the four switches (10, 20, 30, 40) using four switching phases (A, B, C, D). A maximum of two switches out of the four switches (10, 20, 30, 40) change their switching position at a respective transition of subsequent switching phases (A, B, C, D).

Abstract: A multi-current-source comprises a voltage converter (VC), a first current source (CS1) with a first terminal (A1) which is adapted to be coupled to an output (OUT) of a voltage converter (VC) and with a second terminal (B1) which is adapted to be coupled to an input (IN) of the voltage converter (VC), at least a second current source (CS2) with a first terminal (A2) which is adapted to be coupled to the output (OUT) of the voltage converter (VC) and with a second terminal (B2) which is adapted to be coupled to the input (IN) of the voltage converter (VC), wherein the first current source (CS1) being adapted to provide a first load current (Il1) at its first terminal (A1) the first load current (Il1) being regulated to a first constant value and to provide a first unidirectional error current (Ierr1) at its second terminal (B1), wherein the at least one second current source (CS2) being adapted to provide a second load current (I12) at its first terminal (A2), the second load current (I12) being regulated to

Abstract: A voltage converter (10) comprises an input (11) for receiving an input voltage (VIN), a first output (12) for providing a first output voltage (VPOS) and a second output (13) for providing a second output voltage (VNEG). The first output voltage (VPOS) and the second output voltage (VNEG) have opposite polarities. A switching arrangement (14) of the voltage converter (10) is designed to provide energy to an inductor (15) in a charging phase (A) of operation and to provide energy from the inductor (15) to the first output (12) and, via a flying capacitor (16), to the second output (13) in a discharging phase of operation. The first duration (t1) of the charging phase (A) of operation is controlled such that the difference between a first predetermined value and the sum of the absolute value of the first output voltage (VPOS) and of the second output voltage (VNEG) is minimized.

Abstract: A method for DC/DC conversion comprises operating in a Boost mode of operation or in a Buck-Boost mode of operation. Furthermore, the method comprises switching from the Boost mode of operation to the Buck-Boost mode of operation, if a desired value (VOUTR) of an output voltage (VOUT) which is generated from a supply voltage (VIN) by the DC/DC conversion is smaller than a first reference voltage (VR1). The method also comprises switching from the Buck-Boost mode of operation to the Boost mode of operation, if the desired value (VOUTR) is larger than a second reference voltage (VR2).

Abstract: A power source arrangement comprises a controlled and clocked operated power source, that power source providing an output voltage out of a plurality of output voltages in response to a first multiplication factor. One or more regulated current sources are connected to the controlled and clocked operated power source to provide an output current to respective loads. Each of the one or more regulated current sources is adapted to provide a first indication signal upon a regulated operation of the respective current source. The power source arrangement further comprises a dummy power source as well as a dummy current source connected to the dummy power source. The dummy current source receives a load signal corresponding to a voltage drop over the loads connected to the one or more regulated current sources and provides a second indication signal in response thereto.

Abstract: A current source regulator for controlling an output device (Mp) of current source, the output device (Mp) providing an output current (Isrc) to a load. The current source regulator comprises a first feedback loop (1) and second feedback loop (2). The first feedback loop (1) includes a first sensing path to provide a first sensing signal (Is1) for comparison with a first reference to generate a first control signal. The second feedback loop (2) comprises a second sensing path to provide a second sensing signal (Is3, Is3?) for comparison with a second reference (Ib5) to generate a charging current signal (Icharge). The charging current signal (Icharge) is applied to the control signal during a transient state of the current source regulator.

Abstract: An amplifier arrangement comprises a first transistor (18), a first bias transistor (13) and a first field-effect transistor (51). A first input signal (VN) is supplied for amplification to a control terminal of the first transistor (18). The first bias transistor (13) is coupled to the first transistor (18) via a first node (12). The first field-effect transistor (51) is coupled for clamping of a first node voltage (V1) provided at the first node (12).

Abstract: A controlled charge pump comprises a clock operated charge pump having an output terminal to provide an output voltage. A first sub-circuit is coupled to the output terminal of the clocked operated charge pump and adapted to provide a first control signal in response to a comparison of the output voltage with a first reference signal. A second sub-circuit is coupled to the clocked operated charge pump and provides a second control signal in response to a comparison of a switch current within the clocked operated charge pump with a second reference signal. A clock skip controller is adapted to control the mode of operation of the clocked operated charge pump in response to that first and second control signals.

Abstract: A band gap reference circuit comprises a first branch (1) having a first transistor (Q1) and a first temperature-dependent resistive element (S0). A second branch of the band gap reference comprises a second transistor (Q2) having a different size compared to the first transistor (Q1). An output branch (3) comprises a second temperature-dependent resistive element (S1, S2), that second temperature-dependent resistive element being coupled to an output terminal (Vref). At least one of the first and second temperature-dependent resistive elements (S0, S1, S2) comprises a transistor (M2) being arranged in a current path of the respective branch (1, 3) and being controlled such that it operates in a linear region of its characteristics.