Patents by Inventor Pramod Swami

Pramod Swami has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250190746
    Abstract: Disclosed herein are systems and methods for executing a neural network (NN) across multiple processing cores. In an example embodiment, a system includes processing circuitry comprising a first processing core and a second processing core, such that the second processing core is coupled to the first processing core. Prior to executing a current layer of the NN, the second processing core determines a synchronization status of the first processing core with respect to a previous layer of the NN. Next, the second processing core executes the current layer of the NN based on data computed by the first and second processing cores with respect to the previous layer of the NN. Upon executing the current layer of the NN, the second processing core updates the first processing core with a synchronization status of the second processing core with respect to the current layer of the NN.
    Type: Application
    Filed: June 19, 2024
    Publication date: June 12, 2025
    Inventors: Anand Pathak, Anshu Jain, Lakshay Gupta, Pramod Swami
  • Publication number: 20250045572
    Abstract: Disclosed herein are systems and methods for performing post training quantization. A processor obtains fixed-point output values from a layer of an artificial neural network (ANN) wherein the layer includes fixed-point weights determined based on floating-point weights and a weight scaling factor determined based on an output scaling factor. Next, the processor converts the fixed-point output values to floating-point output values based on the output scaling factor. Then, the processor expands a range of floating-point values. Next, the processor calculates a new output scaling factor based on the expanded range of floating-point output values. Finally, the processor stores the new output scaling factor in an associated memory.
    Type: Application
    Filed: January 9, 2024
    Publication date: February 6, 2025
    Inventors: Varun Tripathi, Manu Mathew, Pramod Swami, Kumar Desappan
  • Publication number: 20240338253
    Abstract: Various examples disclosed herein relate to digital signal processing, and more particularly, to processing stages of multi-channel processing pipelines in batches according to an order. A method of such processing is provided and includes retrieving multi-channel data from a memory and processing the multi-channel data with a hardware accelerator implementing a multi-stage processing pipeline for each channel of a plurality of channels. The multi-stage processing pipelines can be arranged in a cyclically descending order based on a total number of stages of each multi-stage processing pipeline. Processing the multi-channel data includes sequentially processing a plurality of batches each including one or more stages from different multi-stage processing pipelines adjacent to each other in the cyclically descending order. Processing the plurality of batches may include processing corresponding ones of the stages in parallel.
    Type: Application
    Filed: July 28, 2023
    Publication date: October 10, 2024
    Inventors: Pramod Swami, Mihir Mody, Deepak Poddar
  • Publication number: 20240202500
    Abstract: Disclosed herein are improved systems and methods for accelerated 2D dilated convolution. A processor determines an offset based on a dilation factor of the 2D dilated convolution. The processor selects rows of data from the 2D input in phases based on the offset and loads an input feature panel without overwriting data that has not yet been consumed by the 2D dilated convolution processor. As the 2D dilated convolution processor performs the convolution iterations, the processor continues to load additional data for the convolution. As the convolution iterations are completed, the processor spaces result of the 2D dilated convolution into a matrix such that results of each phase are spaced based on the offset.
    Type: Application
    Filed: December 16, 2022
    Publication date: June 20, 2024
    Inventors: Varun Tripathi, William Leven, Pramod Swami
  • Publication number: 20240046413
    Abstract: Technology is disclosed herein to execute an inference model by a processor which includes a reshape layer. In an implementation, the reshape layer of the inference model receives an output produced by a previous layer of the inference model and inserts padding into the output, then supplies the padded output as an input to a next layer of the inference model. In an implementation, the inference model includes a stitching layer at the beginning of the inference model and an un-stitch layer at the end of the model. The stitching layer of the inference model stitches together multiple input images into an image batch and supplies the image batch as an input to a subsequent layer. The un-stitch layer receives output from a penultimate layer of the inference model and unstitches the output to produce multiple output images corresponding to the multiple input images.
    Type: Application
    Filed: February 27, 2023
    Publication date: February 8, 2024
    Inventors: Pramod Swami, Anshu Jain, Eppa Praveen Reddy, Kumar Desappan, Soyeb Nagori, Arthur Redfern
  • Patent number: 11831927
    Abstract: The disclosure provides a noise filter. The noise filter includes a motion estimation (ME) engine. The ME receives a current frame and a reference frame. The current frame comprising a current block and the reference frame includes a plurality of reference blocks. The ME engine generates final motion vectors. The current block comprises a plurality of current pixels. A motion compensation unit generates a motion compensated block based on the final motion vectors and the reference frame. The motion compensated block includes a plurality of motion compensated pixels. A weighted average filter multiplies each current pixel of the plurality of current pixels and a corresponding motion compensated pixel of the plurality of motion compensated pixels with a first weight and a second weight respectively. The weighted average filter generates a filtered block. A blockiness removal unit is coupled to the weighted average filter and removes artifacts in the filtered block.
    Type: Grant
    Filed: May 26, 2021
    Date of Patent: November 28, 2023
    Assignee: Texas Instruments Incorporated
    Inventors: Soyeb Nagori, Shyam Jagannathan, Deepak Kumar Poddar, Arun Shankar Kudana, Pramod Swami, Manoj Koul
  • Publication number: 20230252328
    Abstract: Disclosed herein are systems and methods for inference model scheduling of a multi priority inference model system. A processor determines an interrupt flag has been set indicative of a request to interrupt execution of a first inference model in favor of a second inference model. In response to determining that the interrupt flag has been set, the processor determines a state of the execution of the first inference model based on one or more factors. In response to determining the state of the execution is at a preemptable boundary, the processor deactivates the first inference model and activates the second inference model.
    Type: Application
    Filed: January 12, 2023
    Publication date: August 10, 2023
    Inventors: Pramod Swami, Eppa Praveen Reddy, Jesse Villarreal, Kumar Desappan
  • Publication number: 20220327180
    Abstract: Techniques for resizing data including receiving input data values for resizing, placing a first number of data values from a first line of data values of the input data values in a first portion of a first vector, placing the first number of data values from a second line of data values of the input data values in a second portion of the first vector, receiving a first matrix of weights, wherein each weight of the first matrix of weights corresponds to an amount of weight to apply to a data value for a point on a first line of a set of resized data, multiplying the first vector and the first matrix of weights to determine data values for the first line of the set of resized data, and outputting the set of resized data.
    Type: Application
    Filed: September 30, 2021
    Publication date: October 13, 2022
    Inventors: Deepak PODDAR, Soyeb NAGORI, Pramod SWAMI
  • Publication number: 20210289233
    Abstract: The disclosure provides a noise filter. The noise filter includes a motion estimation (ME) engine. The ME receives a current frame and a reference frame. The current frame comprising a current block and the reference frame includes a plurality of reference blocks. The ME engine generates final motion vectors. The current block comprises a plurality of current pixels. A motion compensation unit generates a motion compensated block based on the final motion vectors and the reference frame. The motion compensated block includes a plurality of motion compensated pixels. A weighted average filter multiplies each current pixel of the plurality of current pixels and a corresponding motion compensated pixel of the plurality of motion compensated pixels with a first weight and a second weight respectively. The weighted average filter generates a filtered block. A blockiness removal unit is coupled to the weighted average filter and removes artifacts in the filtered block.
    Type: Application
    Filed: May 26, 2021
    Publication date: September 16, 2021
    Inventors: Soyeb Nagori, Shyam Jagannathan, Deepak Kumar Poddar, Arun Shankar Kudana, Pramod Swami, Manoj Koul
  • Patent number: 11051046
    Abstract: The disclosure provides a noise filter. The noise filter includes a motion estimation (ME) engine. The ME receives a current frame and a reference frame. The current frame comprising a current block and the reference frame includes a plurality of reference blocks. The ME engine generates final motion vectors. The current block comprises a plurality of current pixels. A motion compensation unit generates a motion compensated block based on the final motion vectors and the reference frame. The motion compensated block includes a plurality of motion compensated pixels. A weighted average filter multiplies each current pixel of the plurality of current pixels and a corresponding motion compensated pixel of the plurality of motion compensated pixels with a first weight and a second weight respectively. The weighted average filter generates a filtered block. A blockiness removal unit is coupled to the weighted average filter and removes artifacts in the filtered block.
    Type: Grant
    Filed: August 10, 2020
    Date of Patent: June 29, 2021
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Soyeb Nagori, Shyam Jagannathan, Deepak Kumar Poddar, Arun Shankar Kudana, Pramod Swami, Manoj Koul
  • Publication number: 20200374564
    Abstract: The disclosure provides a noise filter. The noise filter includes a motion estimation (ME) engine. The ME receives a current frame and a reference frame. The current frame comprising a current block and the reference frame includes a plurality of reference blocks. The ME engine generates final motion vectors. The current block comprises a plurality of current pixels. A motion compensation unit generates a motion compensated block based on the final motion vectors and the reference frame. The motion compensated block includes a plurality of motion compensated pixels. A weighted average filter multiplies each current pixel of the plurality of current pixels and a corresponding motion compensated pixel of the plurality of motion compensated pixels with a first weight and a second weight respectively. The weighted average filter generates a filtered block. A blockiness removal unit is coupled to the weighted average filter and removes artifacts in the filtered block.
    Type: Application
    Filed: August 10, 2020
    Publication date: November 26, 2020
    Inventors: Soyeb Nagori, Shyam Jagannathan, Deepak Kumar Poddar, Arun Shankar Kudana, Pramod Swami, Manoj Koul
  • Patent number: 9811607
    Abstract: A device includes an input array register, a determining component and a computing component. The input array register stores a sorted list of n elements as an input array having size n, n being an integer greater than or equal to two. The determining component creates a list of m elements as a mask array having a size m, m being an integer greater than or equal to one, one of the m elements being based on two adjacent of the n elements of the input array. The computing component performs a mathematical operation between the input array and the mask array to generate a list of p elements as an output array having a size p, p being an integer greater than or equal to 0, the p elements identifying unique elements within the n elements.
    Type: Grant
    Filed: February 26, 2015
    Date of Patent: November 7, 2017
    Assignee: Texas Instruments Incorporated
    Inventors: Victor Cheng, Pramod Swami, Prashanth Viswanath
  • Publication number: 20160253365
    Abstract: A device includes an input array register, a determining component and a computing component. The input array register stores a sorted list of n elements as an input array having size n, n being an integer greater than or equal to two. The determining component creates a list of m elements as a mask array having a size m, m being an integer greater than or equal to one, one of the m elements being based on two adjacent of the n elements of the input array. The computing component performs a mathematical operation between the input array and the mask array to generate a list of p elements as an output array having a size p, p being an integer greater than or equal to 0, the p elements identifying unique elements within the n elements.
    Type: Application
    Filed: February 26, 2015
    Publication date: September 1, 2016
    Inventors: Victor Cheng, Pramod Swami, Prashanth Viswanath
  • Publication number: 20150023436
    Abstract: The disclosure provides a noise filter. The noise filter includes a motion estimation (ME) engine. The ME receives a current frame and a reference frame. The current frame comprising a current block and the reference frame includes a plurality of reference blocks. The ME engine generates final motion vectors. The current block comprises a plurality of current pixels. A motion compensation unit generates a motion compensated block based on the final motion vectors and the reference frame. The motion compensated block includes a plurality of motion compensated pixels. A weighted average filter multiplies each current pixel of the plurality current pixels and a corresponding motion compensated pixel of the plurality of motion compensated pixels with a first weight and a second weight respectively. The weighted average filter generates a filtered block. A blockiness removal unit is coupled to the weighted average filter and removes artifacts in the filtered block.
    Type: Application
    Filed: July 22, 2014
    Publication date: January 22, 2015
    Inventors: Soyeb Nagori, Shyam Jagannathan, Deepak Kumar Poddar, Arun Shankar Kudana, Pramod Swami, Manoj Koul