Abstract: A processing system selectively enables and disables a result lookaside buffer (RLB) based on a hit rate tracked by a counter, thereby reducing power consumption for lookups at the result lookaside buffer during periods of low hit rates and improving the overall hit rate for the result lookaside buffer. A controller increments the counter in the event of a hit at the RLB and decrements the counter in the event of a miss at the RLB. If the value of the counter falls below a threshold value, the processing system temporarily disables the RLB for a programmable period of time. After the period of time, the processing system re-enables the RLB and resets the counter to an initial value.

Abstract: A processor selectively adjusts the precision of data for different functional units. Specified functional units of the processor, such as shader processing unit of a graphics processing unit (GPU) include a zeroing module to store, based on the states of corresponding precision flags, a data value of zero at specified portion of an input and/or output data operand. The functional unit then processes the data including the zeroed portion. Because a portion of the data has been zeroed, the functional unit consumes less power during data processing. Furthermore, the precision flags are set such that the reduced precision of the data does not significantly impact a user experience.

Abstract: A processing system selectively enables and disables a result lookaside buffer (RLB) based on a hit rate tracked by a counter, thereby reducing power consumption for lookups at the result lookaside buffer during periods of low hit rates and improving the overall hit rate for the result lookaside buffer. A controller increments the counter in the event of a hit at the RLB and decrements the counter in the event of a miss at the RLB. If the value of the counter falls below a threshold value, the processing system temporarily disables the RLB for a programmable period of time. After the period of time, the processing system re-enables the RLB and resets the counter to an initial value.

Abstract: A processor selectively adjusts the precision of data for different functional units. Specified functional units of the processor, such as shader processing unit of a graphics processing unit (GPU) include a zeroing module to store, based on the states of corresponding precision flags, a data value of zero at specified portion of an input and/or output data operand. The functional unit then processes the data including the zeroed portion. Because a portion of the data has been zeroed, the functional unit consumes less power during data processing. Furthermore, the precision flags are set such that the reduced precision of the data does not significantly impact a user experience.

Abstract: Methods, devices and systems enable prioritizing mobile device access to a communication network during periods of reduced network availability, such as during emergency situations. The mobile device may be configured to detect the existence of an emergency situation locally, on the mobile device. Upon recognizing an emergency situation the mobile device may collect information from various components and/or sensors of the mobile device. Using the collected information, the mobile device may compute a priority for accessing the communication network. Using the computed priority, the mobile device may attempt to access the communication network in a manner that staggers access attempts among all mobile devices to reduce network congestion.

Abstract: Methods, devices and systems enable prioritizing mobile device access to a communication network during periods of reduced network availability, such as during emergency situations. The mobile device may be configured to detect the existence of an emergency situation locally, on the mobile device. Upon recognizing an emergency situation the mobile device may collect information from various components and/or sensors of the mobile device. Using the collected information, the mobile device may compute a priority for accessing the communication network. Using the computed priority, the mobile device may attempt to access the communication network in a manner that staggers access attempts among all mobile devices to reduce network congestion.

Abstract: A microprocessor includes a multiply-accumulate unit (MAU) for performing high-speed signal processing operations. First and second caches provide first and second operands (x, y) directly to the MAU when a multiply-accumulate (MAC) instruction is executed. In addition, a multiplexer is included to select data from either the first and second caches when a normal instruction is executed. A translation look-aside buffer may be included that has page table entries that include additional “reconfigure” and “way” bits to control writing data into the caches. In this manner, the microprocessor may use a conventional n-way set-associative cache to simultaneously access two or more operands.

Abstract: A multi-function device has a user interface with two buttons that are operated using a two-button protocol to generate function messages and instruction messages. Each function message identifies or describes one of the different functions of the device, while each instruction message corresponds to one of the instruction steps for one of the device functions. The user interface generates signals to control presentation of the function and instruction messages. The device also has a message processor that generates the function and instruction messages based on the signals from the user interface as well as a message rendering component to render the function and instruction messages. In one embodiment, the various function and instruction messages are audio messages and the message rendering component is a speaker, although other, non-visual messages could be used instead.

Abstract: This arbitration unit includes a request controller and two bus controllers. The request controller monitors the instruction fetch or data requests and causes the two bus controllers to implement an instruction fetch or data transfer through one of the two memory interfaces based upon a preassigned priority. Based upon at least one address bit or a control bit contained on a memory management translation table, the request controller identifies which of the memory interfaces to utilize to fetch or transfer data. Preferably, one of the storage areas is random-access memory and the other is read-only memory containing program instructions and read-only data.

Abstract: When performing fixed point multiplication with 32 bit operands for example, the product is, in general, represented by a 64 bit number. However, a typical microprocessor may compute the product to only 32 bits. Therefore, the possibility of overflow exists. The present invention provides an indication as to the status of the upper (most significant) 32 bits of the product. This indication may include both "carry" and "overflow" flags, which are unsigned and signed overflow, respectively. The inventive technique is implemented in hardware that is used in conjunction with a Booth recoding multiplier.

Abstract: A TTL to CMOS static input buffer, and method for making same, having a first transistor (32) of a first conductivity type, having a control terminal responsive to a TTL input signal, a first output terminal coupled to a first voltage supply (Vdd) and a second output terminal; a second transistor (31) of a second conductivity type, having a predetermined threshold voltage, a predetermined width-to-length ratio, a control terminal responsive to the TTL input signal, a first output terminal coupled to an output node and a second output terminal coupled to a second voltage supply; a third transistor (33) of the second conductivity type, having a predetermined threshold voltage, a predetermined width-to-length ratio, a control terminal coupled to an intermediate voltage source, a first output terminal coupled to the second terminal of the first transistor and a second output terminal coupled to the output node; and a CMOS inverter (35) having a predetermined threshold voltage Vb; wherein the static input buffer h