Patents by Inventor Pramodchandran N. Variyam

Pramodchandran N. Variyam has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7466259
    Abstract: Methods and apparatus to measure a voltage on an integrated circuit are disclosed. An example method to measure a voltage on an integrated circuit provides a reference signal to a first input of an encoder, provides a signal having a first voltage to a second input of the encoder, varies the reference signal from a second voltage to a third voltage, determines a first time value associated with a change in a state of an output of the encoder during the varying of the reference signal, and measures the first voltage based on the first time value.
    Type: Grant
    Filed: October 27, 2006
    Date of Patent: December 16, 2008
    Assignee: Texas Instruments Incorporated
    Inventor: Pramodchandran N. Variyam
  • Publication number: 20080100484
    Abstract: Methods and apparatus to measure a voltage on an integrated circuit are disclosed. An example method to measure a voltage on an integrated circuit provides a reference signal to a first input of an encoder, provides a signal having a first voltage to a second input of the encoder, varies the reference signal from a second voltage to a third voltage, determines a first time value associated with a change in a state of an output of the encoder during the varying of the reference signal, and measures the first voltage based on the first time value.
    Type: Application
    Filed: October 27, 2006
    Publication date: May 1, 2008
    Inventor: Pramodchandran N. Variyam
  • Patent number: 7259703
    Abstract: The device for detecting and tracking a status of a device under laser trim includes: a series connected string of trim tracking links; and a plurality of detecting devices wherein each detecting device is coupled in parallel with a corresponding trim tracking link. This device allows detection of laser beam to work surface misalignment and the termination of lasing before critical active circuit components can be damaged.
    Type: Grant
    Filed: March 25, 2004
    Date of Patent: August 21, 2007
    Assignee: Texas Instruments Incorporated
    Inventors: Guy J. Shovlin, Melese Teklu, Pramodchandran N. Variyam
  • Patent number: 7006939
    Abstract: A low cost signature test for RF and analog circuits. A model is provided to predict one or more performance parameters characterizing a first electronic circuit produced by a manufacturing process subject to process variation from the output of one or more second electronic circuits produced by the same process in response to a selected test stimulus, and iteratively varying the test stimulus to minimize the error between the predicted performance parameters and corresponding measured values for the performance parameters, for determining an optimized test stimulus. A non-linear model is preferably constructed for relating signature test results employing the optimized test stimulus in manufacturing testing to circuit performance parameters.
    Type: Grant
    Filed: April 18, 2001
    Date of Patent: February 28, 2006
    Assignee: Georgia Tech Research Corporation
    Inventors: Ram Voorakaranam, Abhijit Chatterjee, Pramodchandran N. Variyam, Sasikumar Cherubal, Alfred V. Gomes
  • Patent number: 6865500
    Abstract: The present disclosure relates to a method for testing a circuit having analog components. The method comprises performing a low-cost optimized test on the circuit by applying an optimized input stimulus to the circuit, capturing the circuit response to the input stimulus applied to the circuit, evaluating the circuit response to predict whether the performance parameters of the circuit satisfies predetermined specifications for the circuit, and making a pass/fail determination for the circuit based upon the evaluation of the circuit response.
    Type: Grant
    Filed: May 19, 2000
    Date of Patent: March 8, 2005
    Assignee: Georgia Tech Research Corporation
    Inventors: Pramodchandran N. Variyam, Abhijit Chatterjec
  • Patent number: 6661266
    Abstract: In general, a built-in self test circuit and method is provided that measures error in any periodic signal and, particularly, a Phase Lock Loop (PLL) output clock signal. The circuit includes a short-pulse generator that generates a short-pulse signal having the same frequency as the phase lock loop output clock signal. Accordingly, a delay chain, including a plurality of delay elements, generates N delayed pulses from the short-pulse signal. A hit-pulse generator receives the N delayed pulses and compares each delayed pulse with the phase lock loop output clock signal 2K times, such that the hit-pulse generator also generates a hit-pulse when both signals are high. It also generates a hit count which represents the number of hit-pulses. After each of the N delayed pulses are compared with the clock signal 2k times, a comparator compares a predetermined set of threshold values corresponding to the cumulative distribution of jitter for a PLL clock signal with the hit count.
    Type: Grant
    Filed: November 8, 2000
    Date of Patent: December 9, 2003
    Assignee: Texas Instruments Incorporated
    Inventors: Pramodchandran N. Variyam, Hari Balachandran
  • Publication number: 20020133772
    Abstract: A low cost signature test for RF and analog circuits. A model is provided to predict one or more performance parameters characterizing a first electronic circuit produced by a manufacturing process subject to process variation from the output of one or more second electronic circuits produced by the same process in response to a selected test stimulus, and iteratively varying the test stimulus to minimize the error between the predicted performance parameters and corresponding measured values for the performance parameters, for determining an optimized test stimulus. A non-linear model is preferably constructed for relating signature test results employing the optimized test stimulus in manufacturing testing to circuit performance parameters.
    Type: Application
    Filed: April 18, 2001
    Publication date: September 19, 2002
    Inventors: Ram Voorakaranam, Abhijit Chatterjee, Pramodchandran N. Variyam, Sasikumar Cherubal, Alfred V. Gomes