Abstract: A code protection scheme for controlling access to a memory region in an integrated circuit includes a processor with an instruction pipeline that includes multiple processing stages. A first processing stage receives one or more instructions. A second processing stage receives address information identifying a protected memory region of the memory from the first processing stage and protection information for an identified protected memory region. The protection information indicates a protection state assigned to each protected memory region. Based on the instruction type of the received instruction and the protection information associated with a particular protected memory region, the second processing stage determines whether to enable or disable access to the particular protected memory region by the processor or other external host.

Abstract: A code protection scheme for controlling access to a memory region in an integrated circuit includes a processor with an instruction pipeline that includes multiple processing stages. A first processing stage receives one or more instructions. A second processing stage receives address information identifying a protected memory region of the memory from the first processing stage and protection information for an identified protected memory region. The protection information indicates a protection state assigned to each protected memory region. Based on the instruction type of the received instruction and the protection information associated with a particular protected memory region, the second processing stage determines whether to enable or disable access to the particular protected memory region by the processor or other external host.

Abstract: A code protection scheme for controlling access to a memory region in an integrated circuit includes a processor with an instruction pipeline that includes multiple processing stages. A first processing stage receives one or more instructions. A second processing stage receives address information identifying a protected memory region of the memory from the first processing stage and protection information for an identified protected memory region. The protection information indicates a protection state assigned to each protected memory region. Based on the instruction type of the received instruction and the protection information associated with a particular protected memory region, the second processing stage determines whether to enable or disable access to the particular protected memory region by the processor or other external host.

Abstract: A code protection scheme for controlling access to a memory region in an integrated circuit includes a processor with an instruction pipeline that includes multiple processing stages. A first processing stage receives one or more instructions. A second processing stage receives address information identifying a protected memory region of the memory from the first processing stage and protection information for an identified protected memory region. The protection information indicates a protection state assigned to each protected memory region. Based on the instruction type of the received instruction and the protection information associated with a particular protected memory region, the second processing stage determines whether to enable or disable access to the particular protected memory region by the processor or other external host.

Abstract: A code protection scheme for controlling access to a memory region in an integrated circuit includes a processor with an instruction pipeline that includes multiple processing stages. A first processing stage receives one or more instructions. A second processing stage receives address information identifying a protected memory region of the memory from the first processing stage and protection information for an identified protected memory region. The protection information indicates a protection state assigned to each protected memory region. Based on the instruction type of the received instruction and the protection information associated with a particular protected memory region, the second processing stage determines whether to enable or disable access to the particular protected memory region by the processor or other external host.

Abstract: A cryptographic device includes a key addition module, a first module, and a key module. The key addition module generates an input block based on a cipher key and a plaintext block. The first module generates an output block by performing a plurality of rounds of processing on the input block. The key module, for each of the rounds, provides a round key based on the cipher key. The first module includes an inversion module that, for each of the rounds, performs a matrix inversion operation on first intermediate data to generate second intermediate data. In a first round of the rounds, the first intermediate data is set equal to the input block. The first module also includes a combined operation module that, for each of the rounds, updates the first intermediate data by performing an affine transformation operation and a mix columns operation on the second intermediate data.

Abstract: A code protection scheme for controlling access to a memory region in an integrated circuit includes a processor with an instruction pipeline that includes multiple processing stages. A first processing stage receives one or more instructions. A second processing stage receives address information identifying a protected memory region of the memory from the first processing stage and protection information for an identified protected memory region. The protection information indicates a protection state assigned to each protected memory region. Based on the instruction type of the received instruction and the protection information associated with a particular protected memory region, the second processing stage determines whether to enable or disable access to the particular protected memory region by the processor or other external host.

Abstract: An apparatus includes an encryption module and a first key addition module. The encryption module generates a ciphertext block based on a cipher key and an input block. The encryption module includes a key module configured to provide Nr round keys based on the cipher key, and a cipher module configured to perform Nr cycles of encryption based on the input block and the Nr round keys. The cipher module includes an inversion module configured to generate first intermediate data by performing a matrix inversion operation on the input block, and a combined operation module configured to generate second intermediate data by performing, on the first intermediate data, an affine transformation operation and a mix columns operation. The first key addition module is configured to generate the input block based on the cipher key and a plaintext block. The first key addition module is external to the encryption module.

Abstract: Apparatus having corresponding methods and computer programs comprise: a key input module to receive a first cryptographic key; and a reverse key expansion module to generate a second cryptographic key based on the first cryptographic key, wherein each of the first cryptographic key and the second cryptographic key comprises a plurality of words, and wherein the reverse key expansion module comprises a first word module to generate the first word of the second cryptographic key based on the first word of the first cryptographic key and the last two words of the first cryptographic key, and a remaining word module to generate the remaining words of the second cryptographic key, the remaining word module comprising at least one word module to generate a word of the second cryptographic key based on the corresponding word, and the immediately previous word, of the first cryptographic key.