Abstract: A data transformation system includes clients, which initiate requests for transformation of data between first and second data formats. The system also includes peer transformation servers having data converters and graphs of available transformations between input and output data formats of such servers. The graph includes unidirectional edges, which extend between corresponding pairs of the formats. The servers collectively include one or more converters for each of the edges. The servers receive the requests and select plural intermediate transformations from the first format to plural intermediate formats, and a final transformation from an intermediate format to the second format. Each of the intermediate and final transformations is associated with a corresponding one of the edges. The servers initiate the converters corresponding to the selected transformations, in order to obtain and dispose the data in the second format. A communication network provides communication among the client and servers.

Abstract: A data transformation system includes clients, which initiate requests for transformation of data between first and second data formats. The system also includes peer transformation servers having data converters and graphs of available transformations between input and output data formats of such servers. The graph includes unidirectional edges, which extend between corresponding pairs of the formats. The servers collectively include one or more converters for each of the edges. The servers receive the requests and select plural intermediate transformations from the first format to plural intermediate formats, and a final transformation from an intermediate format to the second format. Each of the intermediate and final transformations is associated with a corresponding one of the edges. The servers initiate the converters corresponding to the selected transformations, in order to obtain and dispose the data in the second format. A communication network provides communication among the client and servers.

Abstract: A floating gate NMOS enhancement mode transistor is utilized in an NMOS SRAM thereby reducing power consumption, size, and circuit complexity of the memory cell. The gate of the load transistor is allowed to float with no galvanic connection to the memory cell circuit. A bias voltage is induced on the gate of the load transistor by capacitances of the gate with the source, the drain, and the bulk semiconductor, and the conductance is maintained below conduction threshold. Gate bias is established by tailoring of the gate capacitances and by the removal of charge using UV light as necessary.