Abstract: A memory module using non-standard configuration memory devices while allowing access by computer systems is disclosed. In one example, according to the JEDEC standard 2M.times.36 configuration, the memory module is comprised of two banks of 1M deep memory blocks. For this JEDEC standard configuration, the computer system will provide four Row Address Strobe (RAS) signals, four Column Address Strobe (CAS) signals, a Write Enable signal, and ten address signals, A0-A9. The RAS and CAS signals allow memory blocks of the memory banks to be accessed. However, with only ten address signals, only 1M deep memory devices having 1M deep memory locations can be addressed. In order to use 2M deep memory devices having 2M deep memory locations, an eleventh address signal (A10) is needed. A logic circuit is thus provided to derive an additional address signal and to provide the needed refresh cycle for the second 1M memory locations of the 2M deep memory devices.