Abstract: Various embodiments may include methods and systems for reconfiguring memory channel routing within a system-on-a-chip (SoC). A method may include obtaining first error information in response to misbehavior in a first memory channel communicatively connected to a network interface unit (NIU) of the SoC. The method may further include storing the first error information in non-volatile memory that is read upon booting of the SoC, and rebooting the SoC including the first memory channel. The method may further include configuring the first memory channel to be communicatively disconnected from the NIU and configuring a second memory channel to be communicatively connected to the NIU in response to reading the stored first error information during reboot.

Abstract: An analog-to-digital converter (ADC) includes a switched capacitor circuit, a comparator, and a control circuit. The switched capacitor circuit has a switch control input and an output, and includes switches coupled to the switch control input and coupled to capacitors. The comparator has an input coupled to the output of the switched capacitor circuit and has an output. The control circuit has a switch control output coupled to the switch control input, has an input coupled to the output of the comparator, and provides switch control signals at the switch control output. Responsive to the switch control signals, the switched capacitor circuit provides an output signal to the comparator that is based on a sample of an analog input signal acquired in a sample acquisition cycle and based on a digital sample value output by the ADC prior to the sample acquisition cycle.

Abstract: A kernel of an HLOS may originate one or more memory refresh requests. Each memory refresh request may have a first memory address range and a size value. A resource power manager may be coupled to the kernel and coupled to memory. The memory may have a plurality of memory ranks. The resource power manger may receive a memory refresh request from the kernel. The resource power manager may then determine if the plurality of memory ranks is either symmetrical or asymmetrical. If the memory ranks are symmetrical, then the resource power manager distributes the memory refresh request evenly and in a parallel manner across the symmetrical memory ranks. If the memory ranks are asymmetrical, then the resource power manager will then determine if the memory refresh request should be one of: a linear only memory refresh; an interleave with linear memory refresh; or an interleave only memory refresh.

Abstract: Various embodiments may include methods and systems for reconfiguring memory channel routing within a system-on-a-chip (SoC). A method may include obtaining first error information in response to misbehavior in a first memory channel communicatively connected to a network interface unit (NIU) of the SoC. The method may further include storing the first error information in non-volatile memory that is read upon booting of the SoC, and rebooting the SoC including the first memory channel. The method may further include configuring the first memory channel to be communicatively disconnected from the NIU and configuring a second memory channel to be communicatively connected to the NIU in response to reading the stored first error information during reboot.

Abstract: A molecular filter that may include a substrate. The substrate may define a first channel, a second channel, at least one slit fluidically coupling the first channel to the second channel, at least one inlet port fluidically coupled to the first channel, at least one recovery port fluidically coupled to the first channel, at least one purge port fluidically coupled to the first channel, and at least one filtrate port fluidically coupled to the second channel. A respective cross-sectional area of each respective slit of the at least one slit in a plane perpendicular to a long axis of the respective slit is smaller than a cross-sectional area of the first channel in a plane perpendicular to a long axis of the first channel.

Abstract: A molecular filter that may include a substrate. The substrate may define a first channel, a second channel, at least one slit fluidically coupling the first channel to the second channel, at least one inlet port fluidically coupled to the first channel, at least one recovery port fluidically coupled to the first channel, at least one purge port fluidically coupled to the first channel, and at least one filtrate port fluidically coupled to the second channel. A respective cross-sectional area of each respective slit of the at least one slit in a plane perpendicular to a long axis of the respective slit is smaller than a cross-sectional area of the first channel in a plane perpendicular to a long axis of the first channel.