Patents by Inventor Pranav Balachander

Pranav Balachander has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240079318
    Abstract: A storage device includes a substrate of a memory package and a first memory die. The substrate includes a controller and a first pin pad, the first pin pad being electrically connected to the controller and defining a data channel for data communications. The first memory die includes a front pin pad electrically connected to the first pin pad of the substrate by way of a first bond wire, a rear pin pad, a redistribution layer electrically connecting the front pin pad and the rear pin pad of the first memory die, and a plurality of memory cells configured to provide non-volatile storage accessible by way of the data channel.
    Type: Application
    Filed: September 6, 2022
    Publication date: March 7, 2024
    Inventors: Md. Sayed Mobin, Nagesh Vodrahalli, Pranav Balachander, Narayanan Terizhandur V
  • Patent number: 11532592
    Abstract: An apparatus is provided that includes a die stack having a first die and a second die disposed above a substrate, and a capacitor die disposed in the die stack between the first die and the second die. The capacitor die includes a plurality of integrated circuit capacitors that are configured to be selectively coupled together to form a desired capacitor value coupled to at least one of the first die and the second die.
    Type: Grant
    Filed: May 8, 2020
    Date of Patent: December 20, 2022
    Assignee: Western Digital Technologies, Inc.
    Inventors: David C. Zhang, Pranav Balachander
  • Publication number: 20210351152
    Abstract: An apparatus is provided that includes a die stack having a first die and a second die disposed above a substrate, and a capacitor die disposed in the die stack between the first die and the second die. The capacitor die includes a plurality of integrated circuit capacitors that are configured to be selectively coupled together to form a desired capacitor value coupled to at least one of the first die and the second die.
    Type: Application
    Filed: May 8, 2020
    Publication date: November 11, 2021
    Applicant: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: David C. Zhang, Pranav Balachander
  • Patent number: 10643676
    Abstract: An apparatus may include a controller die and a group of dies that communicate with each other via a transmission line. The transmission line includes a first portion integrated with a printed circuit board, and a second portion that includes a plurality of wire bonds bonded to input/output pads of the group of dies. The transmission line further includes a resistor circuit connected in series with the first portion and the second portion. The resistor circuit has a resistance value that provides reduced reflection coefficients over the transmission line between the first portion and the second portion. An on-die termination resistor circuit on the controller side is removed, with the inclusion of the resistor circuit.
    Type: Grant
    Filed: September 28, 2018
    Date of Patent: May 5, 2020
    Assignee: Western Digital Technologies, Inc.
    Inventors: Sayed Mobin, John Thomas Contreras, Pranav Balachander
  • Publication number: 20200105318
    Abstract: An apparatus may include a controller die and a group of dies that communicate with each other via a transmission line. The transmission line includes a first portion integrated with a printed circuit board, and a second portion that includes a plurality of wire bonds bonded to input/output pads of the group of dies. The transmission line further includes a resistor circuit connected in series with the first portion and the second portion. The resistor circuit has a resistance value that provides reduced reflection coefficients over the transmission line between the first portion and the second portion. An on-die termination resistor circuit on the controller side is removed, with the inclusion of the resistor circuit.
    Type: Application
    Filed: September 28, 2018
    Publication date: April 2, 2020
    Inventors: Sayed Mobin, John Thomas Contreras, Pranav Balachander
  • Publication number: 20200065270
    Abstract: An apparatus comprising memory having at least one memory die is disclosed. The apparatus may comprises a memory controller. A data bus is coupled to the controller and the memory. A supplemental inductor is coupled to the data bus.
    Type: Application
    Filed: December 31, 2018
    Publication date: February 27, 2020
    Inventors: Md. Sayed Hossain Mobin, John Thomas Contreras, Pranav Balachander