Patents by Inventor Pranav CHAVA

Pranav CHAVA has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230352092
    Abstract: Systems, apparatuses and methods may provide for technology that issues a program pulse to a selected subblock of a NAND memory array, conducts a pulse recovery phase after the program pulse, and shuts down unselected subblocks in the NAND memory array during the pulse recovery phase.
    Type: Application
    Filed: April 28, 2022
    Publication date: November 2, 2023
    Inventors: Tarek Ameen, Shantanu Rajwade, Hsiao Yu Chang, Rohit Shenoy, Pranav Chava, Xin Sun, Pratyush Chandrapati
  • Publication number: 20230178158
    Abstract: Systems, apparatuses and methods may provide for technology that includes a charge pump and applies a program voltage from the charge pump to selected wordlines in the NAND memory. The technology may also conduct a discharge of the program voltage from the charge pump and maintain a connection between the selected wordlines and a pass voltage of the charge pump while the program voltage is being discharged. In one example, the connection between the selected wordlines and the pass voltage prevents the selected wordlines from floating.
    Type: Application
    Filed: December 8, 2021
    Publication date: June 8, 2023
    Inventors: Soo-yong Park, Pranav Chava, Binh Ngo
  • Publication number: 20230086751
    Abstract: Systems, apparatuses, and methods provide for technology that stores a sampled dynamic start voltage value based on a fast to program plane. A current multi-plane program operation is received corresponding to a current cell block and wordline pair associated with a current enabled plane of a plurality of enabled planes. A block list is scanned based on the current cell block and wordline pair. The block list includes a plurality of entries including a reference start voltage corresponding to a reference cell block and wordline pair associated with a reference enabled plane. Additionally, the reference start voltage is reused as a dynamic start voltage in response to finding a match between the current cell block and wordline pair as compared to the reference cell block and wordline pair. Such a match is performed only for a least enabled plane of the plurality of enabled planes.
    Type: Application
    Filed: September 23, 2021
    Publication date: March 23, 2023
    Applicant: Intel Corporation
    Inventors: Sagar Upadhyay, Aliasgar Madraswala, Pranav Chava
  • Publication number: 20210383880
    Abstract: For a nonvolatile (NV) storage media such as NAND (not AND) media that is written by a program and program verify operation, the system can apply a smart prologue operation. A smart prologue operation can selectively apply a standard program prologue, to compute program parameters for a target subblock. The smart prologue operation can selectively apply an accelerated program prologue, applying a previously-computed program parameter for a subsequent subblock of a same block of the NV storage media. Application of a prior program parameter can reduce the need to compute program parameters for the other subblocks.
    Type: Application
    Filed: June 8, 2020
    Publication date: December 9, 2021
    Inventors: Pranav CHAVA, Aliasgar S. MADRASWALA, Sagar UPADHYAY, Bhaskar VENKATARAMAIAH
  • Patent number: 11139036
    Abstract: Provided are an apparatus, memory device, and method for using variable voltages to discharge electrons from a memory array during verify recovery operations. In response to verifying voltages in memory cells of the non-volatile memory array programmed during a programming pulse applying charges to the storage cells, a memory controller concurrently applies voltages on wordlines of the non-volatile memory array to clear the non-volatile memory array of electrons and applies voltages to the bitlines to perform bitline stabilization.
    Type: Grant
    Filed: February 10, 2020
    Date of Patent: October 5, 2021
    Assignee: Intel Corporation
    Inventors: Tarek Ahmed Ameen Beshari, Pranav Chava, Shantanu R. Rajwade, Sagar Upadhyay
  • Publication number: 20210249092
    Abstract: Provided are an apparatus, memory device, and method for using variable voltages to discharge electrons from a memory array during verify recovery operations. In response to verifying voltages in memory cells of the non-volatile memory array programmed during a programming pulse applying charges to the storage cells, a memory controller concurrently applies voltages on wordlines of the non-volatile memory array to clear the non-volatile memory array of electrons and applies voltages to the bitlines to perform bitline stabilization.
    Type: Application
    Filed: February 10, 2020
    Publication date: August 12, 2021
    Inventors: Tarek Ahmed AMEEN BESHARI, Pranav CHAVA, Shantanu R. RAJWADE, Sagar UPADHYAY