Abstract: A unique processor serial number may be utilized to augment a device key seed stored in a non-volatile memory. In this way, a relatively secure system may be enabled that facilitates renewing the device key. An integrated circuit may include a transport demultiplexer and key logic. The key logic communicates with the processor using a secure protocol. The key logic can generate random numbers that may be hashed with the processor serial number and the device key seed to generate a device key. The device key may be provided to a head end to facilitate secure communications between the head end and the client.

Abstract: An apparatus and method for communication between a host CPU and a security co-processor are disclosed, in which a bus having a bi-directional data and command bus, a bi-directional control line, and a uni-directional clock line, is coupled to the CPU and to the co-processor. The bus supports data transfer between the CPU and the co-processor, including read operations and write operations, where each such operation includes a command phase, a data transfer phase, and an error check phase. The CPU and the co-processor have a dual master slave mode wherein either may be master of the bus, while the other is the slave. The bi-directional data and command bus carries command information from the master to the slave 10 during the command phase, and carries data from the master to the slave during the data transfer phase for a write operation, and from the slave to the master for a read operation. The bi-directional control line specifies the start and end of each transfer.

Abstract: An interlaced video signal may be combined with a progressive video signal, such as a graphics signal, by converting the interlaced video signal into a progressive signal. A new frame of the converted progressive signal is constructed from each field of the interlaced signal. The graphics signal is interlaced, then combined with the converted progressive signal. The combined signals may then be transmitted to a display, such as a television set. The interlaced video signal, which is transmitted at twice its incoming speed, remains temporally correct so that operations, such as scaling and 3:2 pulldown, may be performed with minimal resulting artifacts. The small amount of memory used to combine the signals may be embedded in the receiver circuitry.