Abstract: A method and system are disclosed allowing devices to communicate using a highly efficient low pin count bus comprising a set of data lines, a strobe line, and one control line. Command information is transmitted simultaneously with data, the command information being defined by its timing.

Abstract: A cryptographic device is implemented in communication with a host processor to prevent the host processor from performing a standard boot-up procedure until a basic input output system (BIOS) code is authenticated. This is accomplished by a cryptographic device which is addressed by the host processor during execution of a first instruction following a power-up reset. The cryptographic device includes a first integrated circuit (IC) device and a second IC device. The first IC device includes a memory to contain firmware and a root certification key. The second IC device includes logic circuitry to execute a software code to authenticate the BIOS code before permitting execution of the BIOS code by the host processor.

Abstract: A cryptographic device is implemented in communication with a host processor to prevent the host processor from performing a standard boot-up procedure until a basic input output system (BIOS) code is authenticated. This is accomplished by a cryptographic device which is addressed by the host processor during execution of a first instruction following a power-up reset. The cryptographic device includes a first integrated circuit (IC) device and a second IC device. The first IC device includes a memory to contain firmware and a root certification key. The second IC device includes logic circuitry to execute a software code to authenticate the BIOS code before permitting execution of the BIOS code by the host processor.

Abstract: A method and apparatus for configuring the address space of a computer is described. According to the present invention, a computer system has a full address space and includes at least one base unit, at least one expansion unit and a microprocessor core. The microprocessor core issues access addresses. The full address space includes a base address space and an expanded address space. The base address space is addressed by an M bit address and the expanded address space is addressed by an N bit address (N.gtoreq.M). Each base unit is mapped to an address within the base address space, and the base unit address is mirrored in the expanded address space. Each expansion unit is mapped to an address within the expanded address space. An address configuration circuit in the computer system includes an address space remapping circuit for selectively remapping or not remapping base units out of the base address space.