Abstract: A system and method is disclosed for formal verification of software programs that advantageously translates the software, which can have bounded recursion, into a Boolean representation comprised of basic blocks and which applies SAT-based model checking to the Boolean representation.

Abstract: A design verification method for verifying hardware designs utilizing combinational loop logic. A design verification system is provided wherein a model checker receives both a mathematical representation of the functionality of a design and a set of properties against which the mathematical model is to be checked. If the design contains a combinational loop wherein the output directly depends on its own output and must be logically completed within a single bus cycle, then modifications to the model are undertaken. A minimal number of flip-flops are first added to the combinational loop in order to break up the combinational dependency. All of the states of a state machine model of the design are then supplemented with a twin state which is exactly the same as the original state. If the current state is an original state then the next cycle progresses the state machine to twin state of the particular original state.

Abstract: The Complete-1-Distinguishability (C-1-D) property is used for simplifying FSM verification. This property eliminates the need for a traversal of the product machine for the implementation machine and the specification machine. Instead, a much simpler check suffices. This check consists of first obtaining a 1-equivalence mapping between the states of the two machines, and then checking that it is a bisimulation relation. The C-1-D property can be used directly on specifications for which it naturally holds. This property can be enforced on arbitrary FSMs by exposing some of the latch outputs as pseudo-primary outputs during synthesis and verification. In this sense, the synthesis/verification methodology provides another point in the tradeoff curve between constraints-on-synthesis versus complexity-of-verification.

Abstract: A computer system, computer program product, and method for solving a combinational logic verification problem with respect to two combinational circuits includes Boolean SAT checking integrated with binary decision diagrams (BDD) use. A fanout partition of a miter circuit formed from the two combinational circuits is reduced to BDD form, while the fanin partition is represented by SAT clauses. As SAT solutions are evaluated, variables in the cutset between the fanout and fanin partitions are assigned values. In a preferred embodiment, each assignment to a cutset variable is checked against an onset of the BDD prior to continuing with SAT solution seeking.

Abstract: In compiled code simulation, a circuit to be simulated is converted or compiled into an executable so that running the executable produces the same output response as the circuit itself. In a binary decision diagram (BDD)-based compiled code simulator, the simulation executable for the circuit is derived from a BDD-based characteristic function representation of the circuit rather than by the heretofore used translation of Boolean operations in the original circuit into machine instructions.

Abstract: In partial scan testing of integrated circuits, for an arbitrary graph of an integrated circuit, a Boolean function is derived whose satisfying assignments directly correspond to feedback vertex sets of the graph. The Boolean function is then used for determining the minimum cost feedback vertex set. Boolean function representation using Binary Decision Diagrams (BDI)) in logic synthesis is used to solve the problem of representing the Boolean function efficiently, even for large graphs. The determined minimum cost feedback vertex set is used to select those memory elements in the integrated circuit comprising the scan chain.