Patents by Inventor Pranav Ramesh

Pranav Ramesh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250091017
    Abstract: A membrane for separating organic solvents such as methanol and toluene is provided. A plurality methacrylate polymer brushes, e.g., composed of hydroxyethyl methacrylate (HEMA) monomers or aminoethyl methacrylate (AEMA) monomers, are grafted from a crosslinked polyimide support using Single Electron Transfer-Living Radical Polymerization (SET-LRP). The polymer brushes themselves are also crosslinked by ethylene glycol dimethacrylate (EGDMA), triethylene glycol dimethacryalte (TEGDMA) trimesic acid, and/or itaconic acid. These hydrophilic polymeric brush membranes demonstrate pore stiffening and yet also opening, obtaining high selectivity at reasonable permeability and reduced energy requirements for commercially relevant separations, e.g., methanol/toluene. The addition of the crosslinker prevents loss of selectivity as a result of imparting increased rigidity, enabling the membranes to be operated at higher operating pressures for increased throughput.
    Type: Application
    Filed: November 1, 2024
    Publication date: March 20, 2025
    Applicant: RENSSELAER POLYTECHNIC INSTITUTE
    Inventors: Georges BELFORT, Pranav Ramesh, Surya Karla, James Kilduff
  • Publication number: 20240363354
    Abstract: Semiconductor devices and methods for manufacturing the same are provided. The method includes epitaxially growing a doped crystalline silicon-containing layer over a source/drain feature and growing a doped amorphous silicon-containing layer over a field region of a semiconductor layer. The trench is formed in the semiconductor layer and the trench exposes the source/drain feature. The method further includes epitaxially growing an undoped crystalline silicon-containing capping layer over the doped crystalline silicon-containing layer and growing an undoped amorphous silicon-containing layer over the doped silicon-containing amorphous layer. The method further includes selectively removing the doped amorphous silicon-containing layer and the undoped amorphous silicon-containing layer relative to the silicon-containing crystalline capping layer. The method further includes removing the silicon-containing crystalline capping layer to expose the doped silicon-containing crystalline layer.
    Type: Application
    Filed: April 16, 2024
    Publication date: October 31, 2024
    Inventors: He REN, Raman GAIRE, Shi YOU, Pranav RAMESH, Houssam LAZKANI, Shawn THOMAS, Abhishek DUBE, Mehul B. NAIK, Songkram Sonny SRIVATHANAKUL
  • Publication number: 20240234209
    Abstract: Methods for forming a semiconductor structure and semiconductor structures are described. The method comprises patterning a substrate to form a first opening and a second opening, the substrate comprising an n transistor and a p transistor, the first opening over the n transistor and the second opening over the p transistor. The substrate is pre-cleaned. A molybdenum silicide (MoSi) layer is deposited on one or more of the p transistor and the n transistor. A titanium silicide (TiSi) layer is formed on the n transistor and the p transistor. A capping layer may be formed on the titanium silicide (TiSi) layer. The method may be an integrated method performed in a processing chamber without breaking vacuum.
    Type: Application
    Filed: December 19, 2023
    Publication date: July 11, 2024
    Applicant: Applied Materials, Inc.
    Inventors: Avgerinos V. Gelatos, Yang Hu, Thomas Anthony Empante, Gaurav Thareja, Joung Joo Lee, Shi You, Pranav Ramesh, Chi H. Ching, Nicolas Breil