Abstract: An analog-to-digital converter (ADC) includes a switched capacitor circuit, a comparator, and a control circuit. The switched capacitor circuit has a switch control input and an output, and includes switches coupled to the switch control input and coupled to capacitors. The comparator has an input coupled to the output of the switched capacitor circuit and has an output. The control circuit has a switch control output coupled to the switch control input, has an input coupled to the output of the comparator, and provides switch control signals at the switch control output. Responsive to the switch control signals, the switched capacitor circuit provides an output signal to the comparator that is based on a sample of an analog input signal acquired in a sample acquisition cycle and based on a digital sample value output by the ADC prior to the sample acquisition cycle.

Abstract: An analog-to-digital converter (ADC) includes a switched capacitor circuit, a comparator, and a control circuit. The switched capacitor circuit has a switch control input and an output, and includes switches coupled to the switch control input and coupled to capacitors. The comparator has an input coupled to the output of the switched capacitor circuit and has an output. The control circuit has a switch control output coupled to the switch control input, has an input coupled to the output of the comparator, and provides switch control signals at the switch control output. Responsive to the switch control signals, the switched capacitor circuit provides an output signal to the comparator that is based on a sample of an analog input signal acquired in a sample acquisition cycle and based on a digital sample value output by the ADC prior to the sample acquisition cycle.

Abstract: A circuit includes a first gate control circuit including a first time delay element and first and second logic gates. The first time delay element and first and second logic gates receive a pulse width modulation (PWM) signal. The first logic gate includes a first output and second logic gate includes a second output. The circuit also includes a second gate control circuit that includes a second time delay element and third and fourth logic gates. The second time delay element includes an input coupled to the output of the first time delay element. The third logic gate includes a third output, and the fourth logic gate includes a fourth output. A first gate driver receives a first signal from one of the first or third outputs. A second gate driver receives a second signal from one of the second or fourth outputs.

Abstract: A device comprises a digital ramp generator, an oscillator, a power amplifier, a low-noise amplifier (LNA), a mixer, and an intermediate frequency amplifier (IFA). The oscillator generates a chirp signal based on an output from the digital ramp generator. The power amplifier receives the chirp signal and outputs an amplified chirp signal to a transmitter antenna. The LNA receives a reflected chirp signal from a receiver antenna. The mixer receives output of the LNA and combines it with the chirp signal from the oscillator. The IFA receives the mixer output signal and includes a configurable high-pass filter, which has a first cutoff frequency during a first portion of the chirp signal and a second cutoff frequency during a second portion of the chirp signal. In some implementations, the first cutoff frequency is chosen based on a frequency of a blocker signal introduced by couplings between the transmitter and receiver antennas.

Abstract: An analog-to-digital converter (ADC) includes a switched capacitor circuit, a comparator, and a control circuit. The switched capacitor circuit has a switch control input and an output, and includes switches coupled to the switch control input and coupled to capacitors. The comparator has an input coupled to the output of the switched capacitor circuit and has an output. The control circuit has a switch control output coupled to the switch control input, has an input coupled to the output of the comparator, and provides switch control signals at the switch control output. Responsive to the switch control signals, the switched capacitor circuit provides an output signal to the comparator that is based on a sample of an analog input signal acquired in a sample acquisition cycle and based on a digital sample value output by the ADC prior to the sample acquisition cycle.

Abstract: A successive approximation register (SAR) analog-to-digital converter includes a capacitive digital-to-analog converter (CDAC), a comparator, and a SAR control circuit. The comparator is coupled to an output of the CDAC. The SAR control circuit is coupled to an input of the CDAC and to an output of the comparator. The SAR control circuit is configured to provide a feedback signal to the CDAC. The CDAC is configured to apply the feedback signal to form an infinite impulse response filter.

Abstract: A Wi-Fi wake-up receiver that receives wake-up signals encoded using orthogonal frequency division multiplexing based on-off keying (OFDM-OOK) modulation includes receiver circuitry having analog envelope detector circuitry configured to non-linearly down-convert an input signal and provide an energy signal for sampling by an analog-to-digital converter (ADC). A wake-up signal for waking up a main radio in a Wi-Fi device can be based on the digitized energy signal. The receiver circuitry can further include, upstream of the envelope detector circuitry and the ADC in the signal chain, an analog mixer for linearly down-converting the input signal and a low-pass filter for attenuating adjacent-channel interferer (ACI) signals prior to the non-linear down-conversion by the envelope detector circuitry. Sampling of the energy signal rather than the higher-bandwidth input signal yield power savings in the ADC and associated circuitry such as a modem.

Abstract: A successive approximation register (SAR) analog-to-digital converter includes a capacitive digital-to-analog converter (CDAC), a comparator, and a SAR control circuit. The comparator is coupled to an output of the CDAC. The SAR control circuit is coupled to an input of the CDAC and to an output of the comparator. The SAR control circuit is configured to provide a feedback signal to the CDAC. The CDAC is configured to apply the feedback signal to form an infinite impulse response filter.

Abstract: A circuit includes a first gate control circuit including a first time delay element and first and second logic gates. The first time delay element and first and second logic gates receive a pulse width modulation (PWM) signal. The first logic gate includes a first output and second logic gate includes a second output. The circuit also includes a second gate control circuit that includes a second time delay element and third and fourth logic gates. The second time delay element includes an input coupled to the output of the first time delay element. The third logic gate includes a third output, and the fourth logic gate includes a fourth output. A first gate driver receives a first signal from one of the first or third outputs. A second gate driver receives a second signal from one of the second or fourth outputs.

Abstract: A circuit includes a first gate control circuit including a first time delay element and first and second logic gates. The first time delay element and first and second logic gates receive a pulse width modulation (PWM) signal. The first logic gate includes a first output and second logic gate includes a second output. The circuit also includes a second gate control circuit that includes a second time delay element and third and fourth logic gates. The second time delay element includes an input coupled to the output of the first time delay element. The third logic gate includes a third output, and the fourth logic gate includes a fourth output. A first gate driver receives a first signal from one of the first or third outputs. A second gate driver receives a second signal from one of the second or fourth outputs.

Abstract: A circuit includes a first gate control circuit including a first time delay element and first and second logic gates. The first time delay element and first and second logic gates receive a pulse width modulation (PWM) signal. The first logic gate includes a first output and second logic gate includes a second output. The circuit also includes a second gate control circuit that includes a second time delay element and third and fourth logic gates. The second time delay element includes an input coupled to the output of the first time delay element. The third logic gate includes a third output, and the fourth logic gate includes a fourth output. A first gate driver receives a first signal from one of the first or third outputs. A second gate driver receives a second signal from one of the second or fourth outputs.