Abstract: A decimation device has a sampler, a memory and an adder in the decimation stage. The sampler and the adder from a partial sample for storage in the memory at a sample time. At a next sample time the sum of a current sample and the partial sample is output from the decimation stage. The partial sample is formed by adding the first sample to a value equal to twice a second sample obtained after the first sample.

Abstract: A method and apparatus of triggering a device, such a pin limited integrated circuit, to enter a test mode includes embedding a circuit into the device to detect the presence of signal conditions not encountered in normal operation. Pre-defined ones of such signal conditions when detected cause the device to activate one or more test modes by generating one or more internal test signals.

Abstract: A telephone system and method for easing an incoming caller's wait time in queue before being connected to a called party is disclosed. A "ready" signal initiated by the called party via the called party's telephone is provided to the caller's telephone to inform the caller that communication can commence between the caller and the called party. Thus, the caller need not wait with the caller's telephone pressed against his or her ear. Instead, the caller can put the telephone down (off-hook) and go about his or her business until receiving the ready signal. The ready signal can be provided visually and/or audibly. The ready signal can be enabled by the caller. The ready signal can also be terminated by the caller to enable the initiation of communication with the called party. "Ready enable", "ready" and "ready termination" functions can be initiated by pressing specialty keys on a telephone or can be assigned predetermined sequences of keys from a traditional telephone key pad.

Abstract: A logic circuit arrangement for performing synchronous dual word decoding utilizing a programmable logic array which is formed with a reduced number of transistor counts. This is achieved by organizing the AND plane (64) so as to decode only the seven (7) most significant bits of an 8-bit opcode word. A LSB decoder circuit (153) is used for decoding the least significant bit of the opcode word separately and outside of the AND plane. As a result, the amount I.C. chip space required has been substantially reduced.

Abstract: A fast counter includes a clock generator (18), a control circuit (22), and a counting circuit (12). The counting circuit is formed of at least one uniform delay structure (12a, 12b) having a plurality of counter bit cells (58, 60). The uniform delay structure has a regular configuration suitable for very large scale integration. The fast counter is implemented so as to provide minimal propagation delay at relatively low cost.

Abstract: A counter cell includes a latch circuit, control circuit, and a pull-up circuit. The laatch circuit is formed of a first clocked half-latch (32), a second clocked half-latch (34) and an inverter (INV1) for storing a binary output signal. The first clocked half-latch (32) is responsive to a first clockk phase signal for transferring the binary output signal from its input to its output. The second clocked half-latch (34) is responsive to a second clock phase signal for transferring binary output signal from its input to its output. The control circuit is responsive to an input complement signal for selectively passing the first clock phase signal to the first clocked half-latch so as to permit toggling the state of the binary output signal. The pull-up circuit is responsive to the binary output signal and the input complement signal for generating an output complement signal.