Patents by Inventor PRANEETH VADDADI

PRANEETH VADDADI has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240163219
    Abstract: A computerized system of main controller that each node uses to process packets comprising: the main controller that each node uses to process packets, wherein the main controller comprises a plurality of receiving threads while receiving or transmitting a plurality of packets, and wherein when packets are received, a payload of the packet is placed per flow into a payload buffer, which notifies a suitable context queue by identifying a connection and a number of bytes received, and wherein the main controller further comprises: a policy controller configured to handle how and when a request for data and computation is performed, relayed, and cached, based on a localized cost estimation procedure, and a mode selector configured to calibrate a sending rate, a transmission window size, and a payload buffer size, based on a given choice complexity parameter that optimizes for a high throughput, a loss avoidance and a low latency.
    Type: Application
    Filed: June 26, 2023
    Publication date: May 16, 2024
    Inventors: PRAVEEN VADDADI, PRANEETH VADDADI
  • Publication number: 20240152334
    Abstract: In one aspect, a computerized method includes the step of obtaining a binary array, wherein the binary array is utilized for a subsequent set of operations. The method includes the step of performing a dissolution coding on the binary array to yield a one or more generating functions. The method includes the step of codifying the one or more generating functions as a branch-free program to yield an optimal packing of the binary array.
    Type: Application
    Filed: February 7, 2023
    Publication date: May 9, 2024
    Inventors: PRAVEEN VADDADI, PRANEETH VADDADI
  • Publication number: 20240121297
    Abstract: In one aspect, a computerized system comprising: a plurality of nodes interlinked by uniform or non-uniform communication links, wherein each node of the plurality of nodes switches between a propagator mode of operation or non-propagator modes of operation; wherein a first node comprises a computerized synchronization system, wherein the computerized synchronization system synchronizes the data in the plurality of nodes and tracks of all events made on one or more local data units and synchronizes along with the identifiers of the plurality of nodes: a local data storage system that saves and retrieves a plurality of timestamps; a processor to perform basic atomic operations on the plurality of timestamps; an internal clock, wherein a time of the internal clock is modulated by a device; a device which receives messages and data and measures a time of reception and a control time of sending messages and data; a central controller to coordinate all the components in the device; a mode modulator that performs a
    Type: Application
    Filed: May 4, 2023
    Publication date: April 11, 2024
    Inventors: PRAVEEN VADDADI, PRANEETH VADDADI
  • Publication number: 20240086260
    Abstract: In one aspect, a computerized method for scalable, correct, and high-performance asynchronous lockless sharing of a computer resource comprising: determining there is a contention for a shared computer resource by a plurality of competing processes, wherein the plurality of competing processes are competing to access a same portion of the shared resource; adding the plurality of competing processes a priority queue; retrieving a process at a front of the queue of the plurality of competing processes; access a work area of the process at a front of the queue; sharing the work area with other processes of the plurality of competing processes in priority queue; sanitizing the work area to obtain a plurality of code bundles; placing the code bundles into a patchpointer; and processing the patchpointer until the patchpointer is empty.
    Type: Application
    Filed: March 16, 2023
    Publication date: March 14, 2024
    Inventors: PRAVEEN VADDADI, PRANEETH VADDADI
  • Publication number: 20240028303
    Abstract: In one aspect, a method includes the step of applying specified cybernetics to an algorithm development process. The method includes using one or more algebraic topology principles for the generation or discovery of a new algorithm. The method includes generating a homological description of the new algorithm. The method includes providing the new algorithm as a list making algorithm.
    Type: Application
    Filed: July 22, 2022
    Publication date: January 25, 2024
    Inventors: PRAVEEN VADDADI, PRANEETH VADDADI