Abstract: Various example embodiments for supporting loop detection in a communication network are presented. Various example embodiments for supporting loop detection in a communication network may be configured to support loop detection based on use of a recorded route bit string which may be inserted within packets for enabling detection of loops as the packets are communicated over the communication network. Various example embodiments for supporting loop detection in a communication network may be configured to support loop detection for a packet based on inclusion within the packet of a recorded route bit string having bit positions corresponding to nodes of the communication network where the bit positions may be set in a manner indicative of the nodes which have been traversed by the packet.

Abstract: Various example embodiments for supporting processor capabilities are presented herein. Various example embodiments for supporting processor capabilities may be configured to support increased efficiency in utilization of a micro-operations cache (UC) of a processor. Various example embodiments for supporting increased efficiency in utilization of a UC of a processor may be configured to support increased efficiency in utilization of the UC of the processor based on configuration of the processor such that UC lines created by a prediction window (PW) during execution of a set of instructions by the processor are not invalidated on misprediction of a branch instruction in the set of instructions.

Abstract: A router encapsulates a payload of a packet in a generic routing encapsulation (GRE) header that defines a connectionless GRE tunnel. The router also encapsulates the payload and the GRE header in one or more reliable transport headers associated with a connection formed using a reliable transport layer. The router conveys the packet via the connectionless GRE tunnel over the reliable transport layer. In some cases, the GRE header is a network virtualization using GRE (NVGRE) header that allows multiple NVGRE overlays to be multiplexed onto a single IP underlay tunnel. The reliable transport layer can be implemented as Transmission Control Protocol (TCP) layer, a QUIC protocol, a Stream Control Transmission Protocol (SCTP) or a QUIC protocol to establish a set of multiplexed sub-connections or streams over a single connection between two endpoints of the tunnel, or a transport layer security (TLS) cryptographic protocol.

Abstract: Various example embodiments for supporting secure communications via secure sessions in communication systems are presented. Various example embodiments for supporting secure communications via secure sessions in communication systems may be configured to support mechanisms in a session layer protocol which enable communications of any communication protocol at any communication protocol layer to be transported over a session layer session (e.g., tunneling any data link protocol, any network layer protocol, any transport layer protocol, and/or any application layer protocol transparently over the session layer protocol), which enable multiple communications of one or more communication protocols of one or more communication protocol layers to be transported over a single session layer session (e.g.

Abstract: Various example embodiments for supporting quasi-stateful load balancing in communication networks are presented herein. Various example embodiments for supporting quasi-stateful load balancing in communication networks may be configured to reduce or minimize the amount of state information that needs to be maintained by a node for supporting load balancing across outgoing links of the node by reducing or minimizing the number of link pinning state entries that need to be maintained by a node for supporting load balancing across outgoing links of the node. Various example embodiments for supporting quasi-stateful load balancing in communication networks may be configured to reduce or minimize the number of link pinning state entries by deactivating those link pinning state entries associated with flows that remain default mapped to outgoing links and retaining only those link pinning state entries associated with flows that are remapped between outgoing links.

Abstract: Various example embodiments for supporting stateful explicit paths are presented herein. Various example embodiments for supporting stateful explicit paths may be configured to support communication of a packet along a path in an Internet Protocol (IP) network from a first node to a second node, wherein the path includes a set of hops, wherein the packet includes a tuple configured to identify the path, wherein the tuple includes a first IP address of the first node, a second IP address of the second node, and a path identifier of the path, wherein the path identifier of the path is a unique identifier assigned to the path, wherein the communication of the packet along the path from the first node to the second node is supported based on state information configured to map the tuple to a next hop in the set of hops of the path.

Abstract: Various example embodiments for supporting scalability of label switched paths (LSPs) in a label switching network are presented herein. Various example embodiments for supporting scalability of LSPs in a label switching network may be configured to support scalability of LSPs in a Multiprotocol Label Switching (MPLS) network. Various example embodiments for supporting scalability of LSPs in an MPLS network may be configured to support scalability of LSPs of various FEC types. Various example embodiments for supporting scalability of LSPs in an MPLS network may be configured to support scalability of Prefix FEC based LSPs spanning across multiple routing domains. Various example embodiments for supporting scalability of LSPs in an MPLS network may be configured to support scalability of LSPs for various FEC types that enable aggregation of ranges of FECs by aggregate FECs.

Abstract: Various example embodiments for supporting source route compression for source routing are presented herein. Various example embodiments for supporting source route compression for source routing may be configured to support source route compression for source routing based on use of address compression. Various example embodiments for supporting source route compression for source routing based on use of address compression may be configured to support encoding of a set of addresses of a set of hops of a source route by encoding a base address for a first hop of the set of hops and encoding address replacement information for the remaining hops of the set of hops where the address replacement information for the remaining hops of the set of hops can be used to modify the base address to form the addresses for the remaining hops of the set of hops.

Abstract: Various embodiments providing for an indicator (termed the “Traffic Category Indicator,” TCI) to be encoded into packets, different values of which can be used, e.g., to distinguish Traffic Engineered (TE) packets and non-TE packets. In an example embodiment, the TCI can be used, e.g., to configure a network node to implement different packet queues, on each link, for TE packets and non-TE packets. In embodiments corresponding to the DiffSery TE paradigm, a node can be configured to implement different queues within each Forwarding Class for each link, said different queues distinguished by different respective TCI values. Example benefits of TCI include, but are not limited to fate separation of TE and non-TE packets in a node. The TCI concept can beneficially be applied to different packet-switching technologies supporting Source Routing, such as the IP, MPLS, Ethernet, etc.

Abstract: Various example embodiments for supporting affinity groups in a micro-operations cache (UC) of a processor are presented herein. Various example embodiments for supporting affinity groups in a UC of a processor may be configured to support grouping of cache lines of the UC into affinity groups. Various example embodiments for supporting affinity groups in a UC of a processor may be configured to support grouping of cache lines of the UC into affinity groups such that micro-operations (UOPs) of multiple cache lines of an affinity group may be supplied to an execution unit of the processor as a group, thereby enabling execution of the UOPs of the multiple cache lines of the affinity group within a given clock cycle of the processor.

Abstract: An apparatus includes a memory configured to store labels of virtual private networks (VPNs) in a first local label space. The apparatus also includes a processor to assign a first label block identifier (LBI) to a first block of labels in the first local label space and assign a first tuple to a first VPN. The first tuple includes the first LBI and a first label index (LI) that indicates a location of a first label of the first VPN within the first block of labels. The apparatus also includes a transceiver configured to provide the first tuple to routers that allocate second blocks of labels from second local label spaces based on the first tuple. The second routers store the first label at locations in the second label spaces indicated by the first LI.

Abstract: Various example embodiments for supporting processor capabilities are presented herein. Various example embodiments for supporting processor capabilities may be configured to provide a processor configured to support execution of a program that is based on an instruction set architecture of the processor, where the program includes a target instruction configured to mark a beginning of an execution sequence of the program, wherein the target instruction is a target of a branch instruction of the program.

Abstract: Various example embodiments for supporting processor capabilities are presented herein. Various example embodiments may be configured to support a micro-architecture for a micro-operations cache (UC) of a processor. Various example embodiments for supporting a micro-architecture for a UC of a processor may be configured to implement the UC of a processor using an intermediate vector UC (IV-UC). Various example embodiments for supporting an IV-UC for a processor may be configured to support a processor including an IV-UC where the IV-UC includes a micro-operations cache (UC) configured to store a cache line including sets of micro-operations (UOPs) from instructions decoded by the processor and an intermediate vector cache (IVC) configured to store indications of locations of the sets of UOPs in the cache line of the UC for intermediate instructions of the cache line of the UC.

Abstract: Various example embodiments for supporting processor capabilities are presented herein. Various example embodiments may be configured to support a micro-architecture for a micro-operations cache (UC) of a processor. Various example embodiments for supporting a micro-architecture for a UC of a processor may be configured to implement the UC of a processor using a target vector UC (TV-UC). Various example embodiments for supporting a TV-UC for a processor may be configured to support a processor including a TV-UC where the TV-UC includes a micro-operations cache (UC) configured to store a cache line including sets of micro-operations (UOPs) from instructions decoded by the processor and a target vector cache (TVC) configured to store indications of locations of the sets of UOPs in the cache line of the UC.

Abstract: Various example embodiments for supporting sequencing of labeled packets are presented herein. Various example embodiments for supporting sequencing of labeled packets may be configured to support sequencing of labeled packet based on use of a multiprotocol label switching sequence header. Various example embodiments for supporting sequencing of labeled packets may be configured to support sequencing of labeled packet based on use of a multiprotocol label switching sequence header that includes a source identifier of a source of a multiprotocol label switching packet sequence including the multiprotocol label switching packet, a sequence identifier of the multiprotocol label switching packet sequence, and a sequence number of the multiprotocol label switching packet. Various example embodiments for supporting sequencing of labeled packets may be configured to support sequencing of Multiprotocol Label Switching (MPLS) packets.

Abstract: Various example embodiments for supporting a multi-indexed micro-operations cache (MI-UC) in a processor are presented. Various example embodiments for supporting an MI-UC in a processor may be configured to support an MI-UC in which, for a UC line of the MI-UC, multiple indexes into the UC line, for multiple sets of micro-operations (UOPs) stored in the UC line based on decoding of multiple instructions, are supported.

Abstract: A first router transmits a first message including information identifying a first set of transport layer protocols supported by the first router. The first router receives a second message including information identifying a second set of transport layer protocols supported by a second router. A common transport layer protocol is selected from a subset of transport layer protocols that are common to the first and second sets of transport layer protocols. The first router then establishes a border gateway protocol (BGP) session with the second router over the common transport layer protocol. The first message is unicast to the second router or broadcast/multicast over a plurality of links to a plurality of routers that includes the second router. In some cases, the common transport layer protocol is selected by the router having a higher priority, based on preferences, or a combination thereof.

Abstract: Various example embodiments for supporting source routing are presented herein. Various example embodiments for supporting source routing may be configured to support source route compression for source routing. Various example for supporting source route compression for source routing may be configured to support source route compression for source routing based on use of shadow addresses. Various example for supporting source route compression for source routing based on use of shadow addresses may be configured to support source routing of packets based on use of shadow addresses of hops in place of actual addresses of hops to encode source routes within source routed packets, thereby compressing the source routes within the source routed packets and, thus, providing source route compression.

Abstract: Various example embodiments for supporting transport of various protocols over network virtualization technology are presented herein. Various example embodiments for supporting transport of various protocols over network virtualization technology may be configured to support transport of various protocols over network virtualization generic routing encapsulation. Various example embodiments for supporting transport of various protocols over network virtualization technology may be configured to support communication of a packet including a payload and a header of a network virtualization generic routing encapsulation protocol, wherein the payload is based on a protocol other than Ethernet.

Abstract: Various example embodiments for supporting stateful explicit paths are presented herein. Various example embodiments for supporting stateful explicit paths may be configured to support communication of a packet along a path in an Internet Protocol (IP) network from a first node to a second node, wherein the path includes a set of hops, wherein the packet includes a tuple configured to identify the path, wherein the tuple includes a first IP address of the first node, a second IP address of the second node, and a path identifier of the path, wherein the path identifier of the path is a unique identifier assigned to the path, wherein the communication of the packet along the path from the first node to the second node is supported based on state information configured to map the tuple to a next hop in the set of hops of the path.