Abstract: Various example embodiments for supporting sequencing of labeled packets are presented herein. Various example embodiments for supporting sequencing of labeled packets may be configured to support sequencing of labeled packet based on use of a multiprotocol label switching sequence header. Various example embodiments for supporting sequencing of labeled packets may be configured to support sequencing of labeled packet based on use of a multiprotocol label switching sequence header that includes a source identifier of a source of a multiprotocol label switching packet sequence including the multiprotocol label switching packet, a sequence identifier of the multiprotocol label switching packet sequence, and a sequence number of the multiprotocol label switching packet. Various example embodiments for supporting sequencing of labeled packets may be configured to support sequencing of Multiprotocol Label Switching (MPLS) packets.

Abstract: An ingress node includes a transceiver that transmits a packet along a first path from the ingress node to an egress node. The packet includes a globally unique node identifier (node ID) for the ingress node and a path identifier (path ID) of the first path. The transceiver also receives a path congestion notification (path-CN) message in response to congestion along the first path. The path-CN message is addressed to the ingress node based on the node ID and includes the path ID. The ingress node also includes a processor that selects a second path in response to receiving the path-CN message. The transceiver transmits subsequent packets in the flow along the second path. Transit nodes include a transceiver that receives packets including the node ID and the path ID. A processor in the transit node generates the path-CN message based on the node ID.

Abstract: Various example embodiments of a processor cache are presented herein. The processor cache may be configured to support redirection of memory blocks between cache lines, including between cache lines in different sets of the processor cache, thereby improving the efficiency of the processor cache by increasing the utilization of the processor cache and reducing cache misses for the processor cache. The redirection of memory blocks between cache lines may include redirection of a memory block from being stored in a first cache line of a first set of the processor cache which is the default set for the memory block (e.g., when the first set does not have any empty cache lines) to a second cache line of a second set of the processor cache which is not the default set for the memory block (e.g., the second set may be any set having at least one empty cache line).

Abstract: Various example embodiments of a processor cache are presented herein. The processor cache may be configured to support redirection of memory blocks between cache lines, including between cache lines in different sets of the processor cache, thereby improving the efficiency of the processor cache by increasing the utilization of the processor cache and reducing cache misses for the processor cache. The redirection of memory blocks between cache lines may include redirection of a memory block from being stored in a first cache line of a first set of the processor cache which is the default set for the memory block (e.g., when the first set does not have any empty cache lines) to a second cache line of a second set of the processor cache which is not the default set for the memory block (e.g., the second set may be any set having at least one empty cache line).

Abstract: Various example embodiments for supporting processor capabilities are presented herein. Various example embodiments for supporting processor capabilities may be configured to support a multi-mode indexed cache for a processor. Various example embodiments for supporting a multi-mode indexed cache for a processor may be configured to support a multi-mode indexed cache configured as a set associative cache having a plurality of sets, where the cache is configured to support multiple indexing modes for indexing memory blocks such that, for a memory operation for a memory block, the multiple indexing modes are configured to cause selection of different ones of the plurality of sets of the cache for the memory operation for the given memory block.

Abstract: Various example embodiments for supporting a multi-indexed micro-operations cache (MI-UC) in a processor are presented. Various example embodiments for supporting an MI-UC in a processor may be configured to support an MI-UC in which, for a UC line of the MI-UC, multiple indexes into the UC line, for multiple sets of micro-operations (UOPs) stored in the UC line based on decoding of multiple instructions, are supported.

Abstract: Various example embodiments of a processor are presented. Various example embodiments of a processor may be configured to support split programmability of resources of a processor frontend of the processor. Various example embodiments of a processor are configured to support split programmability of resources of a processor frontend of the processor in a manner enabling assignment of split programmable resources of the frontend of the processor to control blocks of a program being executed by the processor. Various example embodiments of a processor are configured to support split programmability of micro-operations (UOPs) cache (UC) resources of the frontend of the processor (which may then be referred to as a split programmable (SP) UC (SP-UC), where it may be referred to as “split” since there are multiple UCs and may be referred to as “programmable” since selection of the active UC from the set of multiple UCs is controllable by the program executed by the processor).

Abstract: Various example embodiments for supporting source routing are presented herein. Various example embodiments for supporting source routing may be configured to support source route compression for source routing. Various example for supporting source route compression for source routing may be configured to support communication of a source routed packet over a path from an ingress node to an egress node over a network, wherein the network includes a set of network elements having a respective set of network element identifiers sharing a common prefix, wherein the source routed packet has encoded therein a source route block including the common prefix and an offset list, wherein the offset list includes a set of offset values associated with respective ones of the network elements of the path and configured to be combined with the common prefix to recover the network element identifiers of the respective ones of the network elements of the path.

Abstract: Various example embodiments for supporting discovery of multicast rendezvous points for multicast trees are presented herein. Various example embodiments for supporting discovery of multicast rendezvous points for multicast trees may be configured to provide a generic capability for discovery of multicast rendezvous points in various types of communication networks which may utilize various communication protocols. Various example embodiments for supporting discovery of multicast rendezvous points for multicast trees may be configured to support discovery of multicast rendezvous points for multicast trees based on advertising of rendezvous point to multicast group mappings for multicast trees.

Abstract: Various example embodiments for supporting operation of a processor cache are presented herein. Various example embodiments for supporting operation of a processor cache may be configured to support operation of an N-way set associative cache based on occupancy state information. Various example embodiments for supporting operation of an N-way set associative cache may be configured to support operation of the N-way set associative cache based on occupancy state information where the occupancy state information may be used to support more efficient memory operations on the N-way set associative cache. Various example embodiments for supporting operation of an N-way set associative cache based on occupancy state information may be configured to maintain occupancy state information for a set of the N-way set associative cache to support more efficient memory operations, including write operations and read operations, on the N-way set associative cache.

Abstract: A node is configured for deployment in an IP network. The node includes a memory configured to store a first identifier that uniquely identifies the node within the IP network. The node also includes a transceiver configured to receive a first IP packet. The node further includes a processor configured to selectively forward the first IP packet based on whether a first recorded route (RR) in the first IP packet includes the first identifier. Selectively forwarding the first IP packet includes dropping the first IP packet in response to the first identifier being in the first IP packet or pushing the first identifier onto the first RR in the first IP packet in response to the first identifier not being in the first IP packet.

Abstract: Various example embodiments for supporting communications for data storage are presented herein. Various example embodiments for supporting communications for data storage may be configured to support communications between a host and a storage element for supporting storage of data in the storage element by the host. Various example embodiments for supporting communications between a host and a storage element may be configured to support communications between a host and a controller of the storage element. Various example embodiments for supporting communications between a host and a controller of a storage element may be configured to support, using a single transport layer connection, communications of multiple queue pairs supporting communications between the host and the controller of the storage element, where each of the queue pairs includes a queue on the host and a queue on the controller of the storage element.

Abstract: Various example embodiments for supporting egress rerouting of data packets in communication devices are presented herein. The egress rerouting of a data packet in a communication device may be performed by rerouting a data packet received via an ingress forwarding element of the communication device from a first egress forwarding element of the communication device associated with a primary next-hop for the data packet to a second egress forwarding element of the communication device associated with a secondary next-hop for the data packet.

Abstract: A network includes a first node having a processor that incorporates a U-turn indicator into a header of an Internet protocol (IP) packet for transmission along a first path towards a second node. The U-turn indicator indicates that the first node expects to receive the IP packet back from the second node. The first node also includes a transceiver that transmits the IP packet including the header having the U-turn indicator along the first path. In some cases, the transceiver (or another transceiver in another node) receives a packet comprising a U-turn indicator. The processor (or another processor in another node) detects the U-turn indicator in a header of the IP packet. The processor forwards the IP packet along a path to a destination node that does not include the node that originally transmitted the IP packet or drops the IP packet depending on whether an alternate path is identified.

Abstract: Various example embodiments for supporting stateless multicast in communication networks are presented. Various example embodiments for supporting stateless multicast in communication networks may be configured to support stateless multicast in multi-domain packet distribution networks. Various example embodiments for supporting stateless multicast in communication networks may be configured to support stateless multicast in multi-domain packet distribution networks which may be based on Internet Protocol (IP). Various example embodiments for supporting stateless multicast in a multi-domain packet distribution network may be configured to support multicast of packets based on use of internal multicast packets for multicast communication of the multicast packets within sub-domains of the multi-domain packet distribution network and use of external multicast packets for unicast communication of the multicast packets across or between sub-domains of the multi-domain packet distribution network.

Abstract: Various example embodiments for supporting egress rerouting of data packets in communication devices are presented herein. The egress rerouting of a data packet in a communication device may be performed by rerouting a data packet received via an ingress forwarding element of the communication device from a first egress forwarding element of the communication device associated with a primary next-hop for the data packet to a second egress forwarding element of the communication device associated with a secondary next-hop for the data packet.

Abstract: Various example embodiments for supporting communication of inter-card control messages in a router chassis are presented herein. The communication of an inter-card control message in a router chassis may be performed using a data packet sent over a switch fabric of the router chassis. The data packet may include a payload and a data packet header, where the payload includes the inter-card control message and the data packet header includes an indication that the data packet includes the inter-card control message. The inter-card control message may be sent over the switch fabric indirectly using a data packet protocol header encapsulating the payload and a switch fabric header encapsulating the data packet protocol header. The inter-card control message may be sent over the switch fabric directly using a switch fabric header encapsulating the payload.

Abstract: In certain embodiments, applications employ data packets having a transport header comprising (i) a port number field encoding a vendor private port number and (ii) a tuple field encoding a vendor unique port number comprising a Vendor Organizationally Unique Identifier (OUI) value and a vendor-specified Vendor Port value. This technique for allocating unique port numbers enables vendors to roll out vendor-proprietary applications at will and without involving any external party. This technique enables faster rollout of vendor-proprietary applications over standard transport protocols without needing to standardize or disclose the details of the application in the public domain. Once standardized, e.g., by the Internet Engineering Task Force (IETF), the technique enables any enterprise to roll out its custom/proprietary applications easily.

Abstract: Various example embodiments for supporting processor capabilities are presented herein. Various example embodiments may be configured to support a micro-architecture for a micro-operations cache (UC) of a processor. Various example embodiments for supporting a micro-architecture for a UC of a processor may be configured to implement the UC of a processor using an intermediate vector UC (IV-UC). Various example embodiments for supporting an IV-UC for a processor may be configured to support a processor including an IV-UC where the IV-UC includes a micro-operations cache (UC) configured to store a cache line including sets of micro-operations (UOPs) from instructions decoded by the processor and an intermediate vector cache (IVC) configured to store indications of locations of the sets of UOPs in the cache line of the UC for intermediate instructions of the cache line of the UC.

Abstract: A first router determines a designated router (DR) from a set of routers that are interconnected by a network based on a border gateway protocol (BGP). The set includes the first router. In response to the first router being the DR, the first router forms adjacencies with non-DR routers from the set and distributes reachability advertisements from the set of routers to the non-DR routers in the set. In response to the first router not being the DR, the first router forms an adjacency with the DR. The first router then conveys reachability advertisements to the DR and receives reachability advertisements from the routers in the set via the DR. The DR is determined based on receiving information at the first router indicating an identity of the DR, e.g., configuration information received from a controller, or by electing a DR based on priority values assigned to the routers and advertised in messages transmitted by the routers.