Abstract: An approach is provided in which the approach applies, by a first node, a first axiom to a set of data points to generate a set of first outputs. The approach applies, by a second node, a second axiom to the set of data points to generate a set of second outputs. The first node and the second node are part of a computer network that includes multiple nodes. The approach computes a first nuance based on a set of disagreements between the set of first outputs and the set of second outputs, and adjusts a reliability of the first node in the computer network based on the first nuance.

Abstract: A mixing pattern system for networks is provided. One or more nodes in a network are analyzed. Grouping the one or more nodes into one or more classes within the network. A computer device analyzes one or more transactions between the one or more nodes in the network that include nodes within similar or distinct classes of the one or more nodes. A computer device identifies one or more mixing patterns associated with one or more transactions between the one or more nodes.

Abstract: A mixing pattern system for networks is provided. One or more nodes in a network are analyzed. Grouping the one or more nodes into one or more classes within the network. A computer device analyzes one or more transactions between the one or more nodes in the network that include nodes within similar or distinct classes of the one or more nodes. A computer device identifies one or more mixing patterns associated with one or more transactions between the one or more nodes.

Abstract: A method for simulating a power consumption associated with a circuit. Once a netlist describing the circuit and an input stimulus for the netlist are obtained, the netlist is partitioned into multiple circuit blocks. Circuit logic models (CLMs) implemented in a hardware description language (HDL) are then obtained for the multiple circuit blocks and a logic netlist is generated from the multiple CLMs. A power vector for a CLM corresponding to a circuit block is calculated using a logic simulator inputting the logic netlist and the input stimulus. Further, a power consumption value is calculated for the circuit block using a circuit simulator and the power vector. The power consumption associated with the circuit is calculated based on the power consumption values for various circuit blocks.

Abstract: According to certain aspects, a system includes frequency measurement devices distributed across a power domain on a chip, wherein the power domain is divided into multiple power sub-domains, and each of the power sub-domains includes a respective subset of the frequency measurement devices. The system also includes a power manager. For each of the power sub-domains, the power manager is configured to receive frequency measurements from the respective subset of the frequency measurement devices, and determine a supply voltage setting for the power sub-domain based on the received frequency measurements from the respective subset of the frequency measurement devices.

Abstract: A particular three-dimensional integrated circuit stack includes a first die including a first bonding interface and a first plurality of interconnect layers arranged according to a first Manhattan wiring scheme. The three-dimensional integrated circuit stack also includes a second die including a second bonding interface and a second plurality of interconnect layers arranged according to a second Manhattan wiring scheme. The first die and the second die stacked with the first bonding interface coupled to the second bonding interface such that the first Manhattan wiring scheme and the second Manhattan wiring scheme are non-Manhattan with respect to each other.

Abstract: A method for simulating a power consumption associated with a circuit. The method includes: obtaining a netlist describing the circuit and an input stimulus for the netlist; partitioning the netlist into multiple circuit blocks; obtaining multiple circuit logic models (CLMs) implemented in a hardware description language (HDL) for the multiple circuit blocks; generating a logic netlist from the multiple CLMs; calculating, using a logic simulator inputting the logic netlist and the input stimulus, a power vector for a CLM corresponding to a first circuit block; calculating, using a circuit simulator and the power vector, a first power consumption value for the first circuit block; and calculating the power consumption associated with the circuit based on the first power consumption value.

Abstract: A system and method of resetting a jam latch circuit includes an activation device. The activation device having respective inputs coupled to each one of several data lines. A first reset device is also included and has a first control input coupled to an output of the activation device. The first reset device having a reset voltage source coupled to an input of the first reset device. A second reset device is also included and has a second control input coupled a control signal. The second reset device being coupled in series with the first reset device. A storage cell is coupled to an output of the second reset device.

Abstract: Error detection apparatus and methods for dynamic logic are provided. Circuit errors are detected by comparing true and complement signals to ensure they are in fact complementary signals. A pseudocomplement technique is used to implement an adder in which distinct logic cones generate the true and complement carry signals. Other embodiments comprising additional features, such as shared logic cone decomposition, are also provided.

Abstract: A system and method of resetting a jam latch circuit includes an activation device. The activation device having respective inputs coupled to each one of several data lines. A first reset device is also included and has a first control input coupled to an output of the activation device. The first reset device having a reset voltage source coupled to an input of the first reset device. A second reset device is also included and has a second control input coupled a control signal. The second reset device being coupled in series with the first reset device. A storage cell is coupled to an output of the second reset device.

Abstract: Error detection apparatus and methods for dynamic logic are provided. Circuit errors are detected by comparing true and complement signals to ensure they are in fact complementary signals. A pseudocomplement technique is used to implement an adder in which distinct logic cones generate the true and complement carry signals. Other embodiments comprising additional features, such as shared logic cone decomposition, are also provided.

Abstract: A method and apparatus for protecting dynamic logic circuits from the effects of noise at the inputs to the dynamic logic circuits is disclosed. Parallel current flow or evaluate paths which couple an output node through a common node to a low voltage or ground rail include extra transistors in the current flow or evaluate path to allow the inputs to be protected while maintaining the operation and integrity of the circuit.

Abstract: A method and apparatus for protecting dynamic logic circuits from the effects of noise at the inputs to the dynamic logic circuits is disclosed. Parallel current flow or evaluate paths which couple an output node through a common node to a low voltage or ground rail include extra transistors in the current flow or evaluate path to allow the inputs to be protected while maintaining the operation and integrity of the circuit.

Abstract: A static latch includes two individual data paths. A first data path is used for passing the data on an output driver for driving a voltage level at the output from the latch toward a logic high or logic low voltage level depending upon the data. A second data path is used for storing the data in a feedback sturcutre so the latch can continue to drive the voltage level at the output node until the next data is loaded into the latch.

Abstract: A domino logic circuit includes a precharge device precharging a precharge node during a precharge phase and a logic block receiving plural input signals to conditionally discharge the precharge node. In this improvement a second precharge device precharges an intermediate node when a particular input signal controls its corresponding logic device to be nonconducting. The intermediate node precharged by this second precharge device may be any intermediate node including the last in a serial chain from the precharge node. This second precharge device may be used with a third precharge device according to the prior art which precharges the intermediate node during the precharge phase. This domino logic circuit may be used with another precharge device controlled by a second input signal different from the first input signal. This additional precharge device may be used to precharge the same intermediate node or another intermediate node.