Patents by Inventor Prapanna Tiwari

Prapanna Tiwari has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method and system for verification of multi-voltage circuit design
    Patent number: 8255859
    Abstract: Multi-voltage circuit design verification segregates design elements into iso-voltage-rail blocks. Information on cross-over connections between the iso-voltage-rail blocks is obtained. Voltage effects are simulated in the circuit design, and, based on the cross-over information, the simulation results are modified. This yields more accurate results of simulations for multi-voltage circuit designs.
    Type: Grant
    Filed: May 18, 2009
    Date of Patent: August 28, 2012
    Assignee: Synopsys, Inc.
    Inventors: Harsh Chilwal, Srikanth Jadcherla, Sriram Kotni, Prapanna Tiwari
  • METHOD AND SYSTEM FOR VERIFICATION OF MULTI-VOLTAGE CIRCUIT DESIGN
    Publication number: 20090228852
    Abstract: Multi-voltage circuit design verification segregates design elements into iso-voltage-rail blocks. Information on cross-over connections between the iso-voltage-rail blocks is obtained. Voltage effects are simulated in the circuit design, and, based on the cross-over information, the simulation results are modified. This yields more accurate results of simulations for multi-voltage circuit designs.
    Type: Application
    Filed: May 18, 2009
    Publication date: September 10, 2009
    Applicant: SYNOPSYS, INC.
    Inventors: Harsh Chilwal, Srikanth Jadcherla, Sriram Kotni, Prapanna Tiwari
  • Method and system for verification of multi-voltage circuit design
    Patent number: 7546566
    Abstract: Multi-voltage circuit design verification segregates design elements into iso-voltage-rail blocks. Information on cross-over connections between the iso-voltage-rail blocks is obtained. Voltage effects are simulated in the circuit design, and, based on the cross-over information, the simulation results are modified. This yields more accurate results of simulations for multi-voltage circuit designs.
    Type: Grant
    Filed: April 5, 2007
    Date of Patent: June 9, 2009
    Assignee: Synopsys, Inc.
    Inventors: Harsh Chilwal, Srikanth Jadcherla, Sriram Kotni, Prapanna Tiwari
  • METHOD AND SYSTEM FOR VERIFICATION OF MULTI-VOLTAGE CIRCUIT DESIGN
    Publication number: 20080250364
    Abstract: Multi-voltage circuit design verification segregates design elements into iso-voltage-rail blocks. Information on cross-over connections between the iso-voltage-rail blocks is obtained. Voltage effects are simulated in the circuit design, and, based on the cross-over information, the simulation results are modified. This yields more accurate results of simulations for multi-voltage circuit designs.
    Type: Application
    Filed: April 5, 2007
    Publication date: October 9, 2008
    Inventors: Harsh Chilwal, Srikanth Jadcherla, Sriram Kotni, Prapanna Tiwari
  • REDUCING TIME TO DESIGN INTEGRATED CIRCUITS INCLUDING PERFORMING ELECTRO-MIGRATION CHECK
    Publication number: 20070079264
    Abstract: The load limit on each path to avoid EM is estimated and provided as an input to various early design stages (such as placement and routing). Each (of one or more) of the early stages may ensure that the load limit is not violated. Techniques such as increasing the path width and inserting additional circuit (e.g., a buffer cell) in the path, may be employed to avoid the EM violations. As a result, unneeded iterations of design stages may be avoided for purposes of EM checks alone.
    Type: Application
    Filed: October 5, 2005
    Publication date: April 5, 2007
    Applicant: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Ananth Goda, Kalpesh SHAH, Prapanna TIWARI, Sugandhini KARUNANIDHI, Venugopal PUVVADA
  • Reducing time to design integrated circuits including performing electro-migration check
    Patent number: 7197730
    Abstract: The load limit on each path to avoid EM is estimated and provided as an input to various early design stages (such as placement and routing). Each (of one or more) of the early stages may ensure that the load limit is not violated. Techniques such as increasing the path width and inserting additional circuit (e.g., a buffer cell) in the path, may be employed to avoid the EM violations. As a result, unneeded iterations of design stages may be avoided for purposes of EM checks alone.
    Type: Grant
    Filed: October 5, 2005
    Date of Patent: March 27, 2007
    Assignee: Texas Instruments Incorporated
    Inventors: Ananth Somayaji Goda, Kalpesh Amrutlal Shah, Prapanna Tiwari, Sugandhini Karunanidhi, Venugopal Puvvada