Patents by Inventor PRASAD BHILAWADI

PRASAD BHILAWADI has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10938200
    Abstract: Described is an apparatus which comprises: one or more signal lines; a transceiver coupled to the one or more signal lines; and a bias generation circuit to provide one or more bias voltages for the transceiver to tri-state the transceiver according to signal attributes of the one or more signal lines.
    Type: Grant
    Filed: February 27, 2017
    Date of Patent: March 2, 2021
    Assignee: Intel Corporation
    Inventors: Amit Kumar Srivastava, Karthik Ns, Raghavendra Devappa Sharma, Dharmaray Nedalgi, Prasad Bhilawadi
  • Patent number: 10193548
    Abstract: Some embodiments include apparatus and methods having a first node to receive a supply voltage, a second node to receive a first bias voltage, a third node to receive ground potential, a first circuit branch coupled between the first and second nodes, and a second circuit branch coupled between the first and third nodes. The first bias voltage is provided to a gate of a first transistor among a plurality of transistors coupled in series. The first and second circuit branches are arranged to provide a second bias voltage to gate of a second transistor among the plurality of transistors. The value of the second bias voltage is based on a value of the first bias voltage.
    Type: Grant
    Filed: September 25, 2017
    Date of Patent: January 29, 2019
    Assignee: Intel Corporation
    Inventors: Mayank Goel, Prasad Bhilawadi, Karthik Ns
  • Publication number: 20180026631
    Abstract: Some embodiments include apparatus and methods having a first node to receive a supply voltage, a second node to receive a first bias voltage, a third node to receive ground potential, a first circuit branch coupled between the first and second nodes, and a second circuit branch coupled between the first and third nodes. The first bias voltage is provided to a gate of a first transistor among a plurality of transistors coupled in series. The first and second circuit branches are arranged to provide a second bias voltage to gate of a second transistor among the plurality of transistors. The value of the second bias voltage is based on a value of the first bias voltage.
    Type: Application
    Filed: September 25, 2017
    Publication date: January 25, 2018
    Inventors: Mayank Goel, Prasad Bhilawadi, Karthik Ns
  • Patent number: 9774324
    Abstract: Some embodiments include apparatus and methods having a first node to receive a supply voltage, a second node to receive a first bias voltage, a third node to receive ground potential, a first circuit branch coupled between the first and second nodes, and a second circuit branch coupled between the first and third nodes. The first bias voltage is provided to a gate of a first transistor among a plurality of transistors coupled in series. The first and second circuit branches are arranged to provide a second bias voltage to gate of a second transistor among the plurality of transistors. The value of the second bias voltage is based on a value of the first bias voltage.
    Type: Grant
    Filed: December 5, 2014
    Date of Patent: September 26, 2017
    Assignee: Intel Corporation
    Inventors: Mayank Goel, Prasad Bhilawadi, Karthik Ns
  • Publication number: 20170170646
    Abstract: Described is an apparatus which comprises: one or more signal lines; a transceiver coupled to the one or more signal lines; and a bias generation circuit to provide one or more bias voltages for the transceiver to tri-state the transceiver according to signal attributes of the one or more signal lines.
    Type: Application
    Filed: February 27, 2017
    Publication date: June 15, 2017
    Inventors: Amit Kumar SRIVASTAVA, Karthik NS, Raghavendra Devappa SHARMA, Dharmaray NEDALGI, Prasad BHILAWADI
  • Patent number: 9601916
    Abstract: Described is an apparatus which comprises: one or more signal lines; a transceiver coupled to the one or more signal lines; and a bias generation circuit to provide one or more bias voltages for the transceiver to tri-state the transceiver according to signal attributes of the one or more signal lines.
    Type: Grant
    Filed: September 11, 2014
    Date of Patent: March 21, 2017
    Assignee: Intel Corporation
    Inventors: Amit Kumar Srivastava, Karthik Ns, Raghavendra Devappa Sharma, Dharmaray Nedalgi, Prasad Bhilawadi
  • Publication number: 20160164515
    Abstract: Some embodiments include apparatus and methods having a first node to receive a supply voltage, a second node to receive a first bias voltage, a third node to receive ground potential, a first circuit branch coupled between the first and second nodes, and a second circuit branch coupled between the first and third nodes. The first bias voltage is provided to a gate of a first transistor among a plurality of transistors coupled in series. The first and second circuit branches are arranged to provide a second bias voltage to gate of a second transistor among the plurality of transistors. The value of the second bias voltage is based on a value of the first bias voltage.
    Type: Application
    Filed: December 5, 2014
    Publication date: June 9, 2016
    Inventors: Mayank Goel, Prasad Bhilawadi, Karthik Ns
  • Publication number: 20160079747
    Abstract: Described is an apparatus which comprises: one or more signal lines; a transceiver coupled to the one or more signal lines; and a bias generation circuit to provide one or more bias voltages for the transceiver to tri-state the transceiver according to signal attributes of the one or more signal lines.
    Type: Application
    Filed: September 11, 2014
    Publication date: March 17, 2016
    Inventors: Amit Kumar Srivastava, KARTHIK NS, RAGHAVENDRA DEVAPPA SHARMA, DHARMARAY NEDALGI, PRASAD BHILAWADI