Patents by Inventor Prasad Bhosale

Prasad Bhosale has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10242872
    Abstract: A method for reworking a semiconductor device includes, in a pattern stack formed on an interlevel dielectric (ILD) layer, polishing the pattern stack to remove a top hardmask layer of the pattern stack. Each hardmask layer of the pattern stack is selectively wet etched to remaining layers of the pattern stack and the ILD layer. A reworked pattern stack is reformed on the ILD layer.
    Type: Grant
    Filed: March 21, 2017
    Date of Patent: March 26, 2019
    Assignee: International Business Machines Corporation
    Inventors: John C. Arnold, Prasad Bhosale, Donald F. Canaperi, Raghuveer R. Patlolla, Cornelius B. Peethala, Hosadurga Shobha, Theodorus E. Standaert
  • Publication number: 20180349538
    Abstract: A method of electrical device manufacturing that includes measuring a first plurality of dimensions and electrical performance from back end of the line (BEOL) structures; and comparing the first plurality of dimensions with a second plurality of dimensions from a process assumption model to determine dimension variations by machine vision image processing. The method further includes providing a plurality of scenarios for process modifications by applying machine image learning to the dimension variations and electrical variations in the in line electrical measurements from the process assumption model. The method further includes receiving production dimension measurements and electrical measurements at a manufacturing prediction actuator. The at least one of the dimensions or electrical measurements received match one of the plurality of scenarios the manufacturing prediction actuator using the plurality of scenarios for process modifications effectuates a process change.
    Type: Application
    Filed: December 7, 2017
    Publication date: December 6, 2018
    Inventors: Prasad Bhosale, Michael Rizzolo, Chih-Chao Yang
  • Publication number: 20180349535
    Abstract: A method of electrical device manufacturing that includes measuring a first plurality of dimensions and electrical performance from back end of the line (BEOL) structures; and comparing the first plurality of dimensions with a second plurality of dimensions from a process assumption model to determine dimension variations by machine vision image processing. The method further includes providing a plurality of scenarios for process modifications by applying machine image learning to the dimension variations and electrical variations in the in line electrical measurements from the process assumption model. The method further includes receiving production dimension measurements and electrical measurements at a manufacturing prediction actuator. The at least one of the dimensions or electrical measurements received match one of the plurality of scenarios the manufacturing prediction actuator using the plurality of scenarios for process modifications effectuates a process change.
    Type: Application
    Filed: May 31, 2017
    Publication date: December 6, 2018
    Inventors: Prasad Bhosale, Michael Rizzolo, Chih-Chao Yang
  • Patent number: 10096769
    Abstract: A substantially flat bottom electrode for magnetoresistive random access memory (MRAM) devices includes three components: a recessed bulk conductive material such as copper, a conductive liner lining the recess, and a cap layer, wherein the conductive liner is a harder material than the cap layer. The cap layer and the dielectric layer are coplanar having a height differential of less than 3 nanometers. The conductive liner has a lower chemical mechanical planarization removal rate. Also provided are processes for forming the bottom electrode.
    Type: Grant
    Filed: March 10, 2017
    Date of Patent: October 9, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Prasad Bhosale, Raghuveer R. Patlolla, Michael Rizzolo, Chih-Chao Yang
  • Publication number: 20180287051
    Abstract: A substantially flat bottom electrode for magnetoresistive random access memory (MRAM) devices includes three components: a recessed bulk conductive material such as copper, a conductive liner lining the recess, and a cap layer, wherein the conductive liner is a harder material than the cap layer. The cap layer and the dielectric layer are coplanar having a height differential of less than 3 nanometers. The conductive liner has a lower chemical mechanical planarization removal rate. Also provided are processes for forming the bottom electrode.
    Type: Application
    Filed: June 5, 2018
    Publication date: October 4, 2018
    Inventors: Prasad Bhosale, Raghuveer R. Patlolla, Michael Rizzolo, Chih-Chao Yang
  • Publication number: 20180277369
    Abstract: A method for reworking a semiconductor device includes, in a pattern stack formed on an interlevel dielectric (ILD) layer, polishing the pattern stack to remove a top hardmask layer of the pattern stack. Each hardmask layer of the pattern stack is selectively wet etched to remaining layers of the pattern stack and the ILD layer. A reworked pattern stack is reformed on the ILD layer.
    Type: Application
    Filed: March 21, 2017
    Publication date: September 27, 2018
    Inventors: John C. Arnold, Prasad Bhosale, Donald F. Canaperi, Raghuveer R. Patlolla, Cornelius B. Peethala, Hosadurga Shobha, Theodorus E. Standaert
  • Publication number: 20180261759
    Abstract: A substantially flat bottom electrode for magnetoresistive random access memory (MRAM) devices includes three components: a recessed bulk conductive material such as copper, a conductive liner lining the recess, and a cap layer, wherein the conductive liner is a harder material than the cap layer. The cap layer and the dielectric layer are coplanar having a height differential of less than 3 nanometers. The conductive liner has a lower chemical mechanical planarization removal rate. Also provided are processes for forming the bottom electrode.
    Type: Application
    Filed: March 10, 2017
    Publication date: September 13, 2018
    Inventors: Prasad Bhosale, Raghuveer R. Patlolla, Michael Rizzolo, Chih-Chao Yang