Patents by Inventor Prasad Bhosale

Prasad Bhosale has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10756990
    Abstract: This disclosure describes, in some examples, techniques for improving, adjusting, and/or optimizing the infrastructure of a network. This disclosure also describes techniques for monitoring a network using a ping utility integrated into the monitoring platform described herein at the application service level. This disclosure further describes techniques for monitoring database performance through data collected by, for example, database scripts that capture the response time for queries.
    Type: Grant
    Filed: November 28, 2017
    Date of Patent: August 25, 2020
    Assignee: Equinix, Inc.
    Inventors: Vishnu Prasad Chakkassery Vidyadharan, Vaibhav Pralhad Bhosale, Loveneesh Bansal, Greg Alan Ogle
  • Publication number: 20200251386
    Abstract: Metal interconnect structures are reworked to address possible voids or other defects. Etching of initially deposited interconnect metal to open voids is followed by reflow to accumulate interconnect metal at the bottoms of trenches. Additional interconnect metal is deposited over the initially deposited interconnect metal by electroplating and/or electroless plating. Additional diffusion barrier material may be deposited and patterned prior to deposition of the additional interconnect material.
    Type: Application
    Filed: April 24, 2020
    Publication date: August 6, 2020
    Inventors: Prasad Bhosale, Terry A. Spooner, Chih-Chao Yang, Lawrence A. Clevenger
  • Publication number: 20200243383
    Abstract: The present invention provides interconnects with self-forming wrap-all-around graphene barrier layer. In one aspect, a method of forming an interconnect structure is provided. The method includes: patterning at least one trench in a dielectric; forming an interconnect in the at least one trench embedded in the dielectric; and forming a wrap-all-around graphene barrier surrounding the interconnect. An interconnect structure having a wrap-all-around graphene barrier is also provided.
    Type: Application
    Filed: January 30, 2019
    Publication date: July 30, 2020
    Inventors: Huai Huang, Takeshi Nogami, Alfred Grill, Benjamin D. Briggs, Nicholas A. Lanzillo, Christian Lavoie, Devika Sil, Prasad Bhosale, James Kelly
  • Patent number: 10658235
    Abstract: Metal interconnect structures are reworked to address possible voids or other defects. Etching of initially deposited interconnect metal to open voids is followed by reflow to accumulate interconnect metal at the bottoms of trenches. Additional interconnect metal is deposited over the initially deposited interconnect metal by electroplating and/or electroless plating. Additional diffusion barrier material may be deposited and patterned prior to deposition of the additional interconnect material.
    Type: Grant
    Filed: June 21, 2018
    Date of Patent: May 19, 2020
    Assignee: International Business Machines Corporation
    Inventors: Prasad Bhosale, Terry A. Spooner, Chih-Chao Yang, Lawrence A. Clevenger
  • Publication number: 20200089831
    Abstract: A method of electrical device manufacturing that includes measuring a first plurality of dimensions and electrical performance from back end of the line (BEOL) structures; and comparing the first plurality of dimensions with a second plurality of dimensions from a process assumption model to determine dimension variations by machine vision image processing. The method further includes providing a plurality of scenarios for process modifications by applying machine image learning to the dimension variations and electrical variations in the in line electrical measurements from the process assumption model. The method further includes receiving production dimension measurements and electrical measurements at a manufacturing prediction actuator. The at least one of the dimensions or electrical measurements received match one of the plurality of scenarios the manufacturing prediction actuator using the plurality of scenarios for process modifications effectuates a process change.
    Type: Application
    Filed: November 15, 2019
    Publication date: March 19, 2020
    Inventors: Prasad Bhosale, Michael Rizzolo, Chih-Chao Yang
  • Patent number: 10585998
    Abstract: A method of electrical device manufacturing that includes measuring a first plurality of dimensions and electrical performance from back end of the line (BEOL) structures; and comparing the first plurality of dimensions with a second plurality of dimensions from a process assumption model to determine dimension variations by machine vision image processing. The method further includes providing a plurality of scenarios for process modifications by applying machine image learning to the dimension variations and electrical variations in the in line electrical measurements from the process assumption model. The method further includes receiving production dimension measurements and electrical measurements at a manufacturing prediction actuator. The at least one of the dimensions or electrical measurements received match one of the plurality of scenarios the manufacturing prediction actuator using the plurality of scenarios for process modifications effectuates a process change.
    Type: Grant
    Filed: December 7, 2017
    Date of Patent: March 10, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Prasad Bhosale, Michael Rizzolo, Chih-Chao Yang
  • Publication number: 20200053128
    Abstract: An example operation may include one or more of identifying a current tool configuration used by a tool device to construct semiconductor devices, retrieving a smart contract stored in a blockchain to identify whether an updated tool configuration exists, responsive to identifying the updated tool configuration, transmitting an update that includes the updated tool configuration to the tool device, and responsive to receiving the updated tool configuration at the tool device, initiating construction of the semiconductor devices.
    Type: Application
    Filed: August 13, 2018
    Publication date: February 13, 2020
    Inventors: Prasad Bhosale, Nicholas A. Lanzillo, Michael Rizzolo, Chih-Chao Yang
  • Patent number: 10558541
    Abstract: This disclosure describes, in some examples, a monitoring platform to provide integrated system that ingests, correlates, and provides alerts for monitored data relating to nodes, which may include applications, services, containers, and network components. In one example, this disclosure describes a method that includes receiving, by a computing system in a network, criticality information about a node included within the network; identifying, by the computing system, a status change associated with the node; determining, by the computing system and based on the criticality information about the node, an impact resulting from the status change; determining, by the computing system and based on the determined impact, whether to communicate information about the determined impact; and sending, by the computing system, an alert about the determined impact.
    Type: Grant
    Filed: September 22, 2017
    Date of Patent: February 11, 2020
    Assignee: Equinix, Inc.
    Inventors: Vishnu Prasad Chakkassery Vidyadharan, Loveneesh Bansal, Vaibhav Pralhad Bhosale, Greg Alan Ogle
  • Publication number: 20190393085
    Abstract: Metal interconnect structures are reworked to address possible voids or other defects. Etching of initially deposited interconnect metal to open voids is followed by reflow to accumulate interconnect metal at the bottoms of trenches. Additional interconnect metal is deposited over the initially deposited interconnect metal by electroplating and/or electroless plating. Additional diffusion barrier material may be deposited and patterned prior to deposition of the additional interconnect material.
    Type: Application
    Filed: June 21, 2018
    Publication date: December 26, 2019
    Inventors: Prasad Bhosale, Terry A. Spooner, Chih-Chao Yang, Lawrence A. Clevenger
  • Patent number: 10461248
    Abstract: A substantially flat bottom electrode for magnetoresistive random access memory (MRAM) devices includes three components: a recessed bulk conductive material such as copper, a conductive liner lining the recess, and a cap layer, wherein the conductive liner is a harder material than the cap layer. The cap layer and the dielectric layer are coplanar having a height differential of less than 3 nanometers. The conductive liner has a lower chemical mechanical planarization removal rate. Also provided are processes for forming the bottom electrode.
    Type: Grant
    Filed: June 5, 2018
    Date of Patent: October 29, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Prasad Bhosale, Raghuveer R. Patlolla, Michael Rizzolo, Chih-Chao Yang
  • Patent number: 10303829
    Abstract: A method of electrical device manufacturing that includes measuring a first plurality of dimensions and electrical performance from back end of the line (BEOL) structures; and comparing the first plurality of dimensions with a second plurality of dimensions from a process assumption model to determine dimension variations by machine vision image processing. The method further includes providing a plurality of scenarios for process modifications by applying machine image learning to the dimension variations and electrical variations in the in line electrical measurements from the process assumption model. The method further includes receiving production dimension measurements and electrical measurements at a manufacturing prediction actuator. The at least one of the dimensions or electrical measurements received match one of the plurality of scenarios the manufacturing prediction actuator using the plurality of scenarios for process modifications effectuates a process change.
    Type: Grant
    Filed: May 31, 2017
    Date of Patent: May 28, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Prasad Bhosale, Michael Rizzolo, Chih-Chao Yang
  • Patent number: 10242872
    Abstract: A method for reworking a semiconductor device includes, in a pattern stack formed on an interlevel dielectric (ILD) layer, polishing the pattern stack to remove a top hardmask layer of the pattern stack. Each hardmask layer of the pattern stack is selectively wet etched to remaining layers of the pattern stack and the ILD layer. A reworked pattern stack is reformed on the ILD layer.
    Type: Grant
    Filed: March 21, 2017
    Date of Patent: March 26, 2019
    Assignee: International Business Machines Corporation
    Inventors: John C. Arnold, Prasad Bhosale, Donald F. Canaperi, Raghuveer R. Patlolla, Cornelius B. Peethala, Hosadurga Shobha, Theodorus E. Standaert
  • Publication number: 20180349538
    Abstract: A method of electrical device manufacturing that includes measuring a first plurality of dimensions and electrical performance from back end of the line (BEOL) structures; and comparing the first plurality of dimensions with a second plurality of dimensions from a process assumption model to determine dimension variations by machine vision image processing. The method further includes providing a plurality of scenarios for process modifications by applying machine image learning to the dimension variations and electrical variations in the in line electrical measurements from the process assumption model. The method further includes receiving production dimension measurements and electrical measurements at a manufacturing prediction actuator. The at least one of the dimensions or electrical measurements received match one of the plurality of scenarios the manufacturing prediction actuator using the plurality of scenarios for process modifications effectuates a process change.
    Type: Application
    Filed: December 7, 2017
    Publication date: December 6, 2018
    Inventors: Prasad Bhosale, Michael Rizzolo, Chih-Chao Yang
  • Publication number: 20180349535
    Abstract: A method of electrical device manufacturing that includes measuring a first plurality of dimensions and electrical performance from back end of the line (BEOL) structures; and comparing the first plurality of dimensions with a second plurality of dimensions from a process assumption model to determine dimension variations by machine vision image processing. The method further includes providing a plurality of scenarios for process modifications by applying machine image learning to the dimension variations and electrical variations in the in line electrical measurements from the process assumption model. The method further includes receiving production dimension measurements and electrical measurements at a manufacturing prediction actuator. The at least one of the dimensions or electrical measurements received match one of the plurality of scenarios the manufacturing prediction actuator using the plurality of scenarios for process modifications effectuates a process change.
    Type: Application
    Filed: May 31, 2017
    Publication date: December 6, 2018
    Inventors: Prasad Bhosale, Michael Rizzolo, Chih-Chao Yang
  • Patent number: 10096769
    Abstract: A substantially flat bottom electrode for magnetoresistive random access memory (MRAM) devices includes three components: a recessed bulk conductive material such as copper, a conductive liner lining the recess, and a cap layer, wherein the conductive liner is a harder material than the cap layer. The cap layer and the dielectric layer are coplanar having a height differential of less than 3 nanometers. The conductive liner has a lower chemical mechanical planarization removal rate. Also provided are processes for forming the bottom electrode.
    Type: Grant
    Filed: March 10, 2017
    Date of Patent: October 9, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Prasad Bhosale, Raghuveer R. Patlolla, Michael Rizzolo, Chih-Chao Yang
  • Publication number: 20180287051
    Abstract: A substantially flat bottom electrode for magnetoresistive random access memory (MRAM) devices includes three components: a recessed bulk conductive material such as copper, a conductive liner lining the recess, and a cap layer, wherein the conductive liner is a harder material than the cap layer. The cap layer and the dielectric layer are coplanar having a height differential of less than 3 nanometers. The conductive liner has a lower chemical mechanical planarization removal rate. Also provided are processes for forming the bottom electrode.
    Type: Application
    Filed: June 5, 2018
    Publication date: October 4, 2018
    Inventors: Prasad Bhosale, Raghuveer R. Patlolla, Michael Rizzolo, Chih-Chao Yang
  • Publication number: 20180277369
    Abstract: A method for reworking a semiconductor device includes, in a pattern stack formed on an interlevel dielectric (ILD) layer, polishing the pattern stack to remove a top hardmask layer of the pattern stack. Each hardmask layer of the pattern stack is selectively wet etched to remaining layers of the pattern stack and the ILD layer. A reworked pattern stack is reformed on the ILD layer.
    Type: Application
    Filed: March 21, 2017
    Publication date: September 27, 2018
    Inventors: John C. Arnold, Prasad Bhosale, Donald F. Canaperi, Raghuveer R. Patlolla, Cornelius B. Peethala, Hosadurga Shobha, Theodorus E. Standaert
  • Publication number: 20180261759
    Abstract: A substantially flat bottom electrode for magnetoresistive random access memory (MRAM) devices includes three components: a recessed bulk conductive material such as copper, a conductive liner lining the recess, and a cap layer, wherein the conductive liner is a harder material than the cap layer. The cap layer and the dielectric layer are coplanar having a height differential of less than 3 nanometers. The conductive liner has a lower chemical mechanical planarization removal rate. Also provided are processes for forming the bottom electrode.
    Type: Application
    Filed: March 10, 2017
    Publication date: September 13, 2018
    Inventors: Prasad Bhosale, Raghuveer R. Patlolla, Michael Rizzolo, Chih-Chao Yang