Patents by Inventor Prasad Jonnalagadda

Prasad Jonnalagadda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10832772
    Abstract: The present disclosure relates to an apparatus for a memristor crossbar array. The apparatus comprises an adjustment circuit configured for receiving a current that is output by the array at an actual operating condition of the array. The apparatus further comprises a calibration circuit configured for determining a measured or modelled variation of output currents of the array at the actual operating condition with respect to a reference operating condition, wherein the adjustment circuit is configured to adjust the output current by the variation.
    Type: Grant
    Filed: January 3, 2019
    Date of Patent: November 10, 2020
    Assignee: International Business Machines Corporation
    Inventors: Iason Giannopoulos, Abu Sebastian, Evangelos Stavros Eleftheriou, Manuel Le Gallo-Bourdeau, Vara Sudananda Prasad Jonnalagadda
  • Publication number: 20200259712
    Abstract: Systems and methods for rollback of model-based provisioned network device configuration including a memory capable of storing a model-based provisioned data template that includes a data template sequence. Data associated with a request to transmit a target object request message are received and transmitted following a retrieval message that determines pre-configuration data of the target device. The pre-configuration data is stored and the target object request message is sent specifying CRUD semantics. A notification is received indicating an outcome of the execution and, if the execution outcome is unsuccessful, a rollback stack is retrieved that specifies CRUD semantics and the pre-configuration parameters are retrieved to restore the target device to a pre-request state. If the execution outcome is successful, a second target object request message is retrieved from a list of target devices.
    Type: Application
    Filed: February 7, 2020
    Publication date: August 13, 2020
    Applicant: Affirmed Networks, Inc.
    Inventors: Prasad JONNALAGADDA, Livin Wilson VALIYAVEETIL, Venu GOLI
  • Publication number: 20200118624
    Abstract: The present disclosure relates to an apparatus for a memristor crossbar array. The apparatus comprises an adjustment circuit configured for receiving a current that is output by the array at an actual operating condition of the array. The apparatus further comprises a calibration circuit configured for determining a measured or modelled variation of output currents of the array at the actual operating condition with respect to a reference operating condition, wherein the adjustment circuit is configured to adjust the output current by the variation.
    Type: Application
    Filed: January 3, 2019
    Publication date: April 16, 2020
    Inventors: Iason Giannopoulos, Abu Sebastian, Evangelos Stavros Eleftheriou, Manuel Le Gallo-Bourdeau, Vara Sudananda Prasad Jonnalagadda
  • Patent number: 10395732
    Abstract: Apparatus including: memory cell unit(s) having a variable-resistance channel component (CC) extending between first and second supply terminals for supplying read and write (R/W) signals to the unit in respective R/W modes, and resistive memory elements (RMEs) arranged along the CC, RME includes resistive memory material (RMM), extending along a respective channel segment (CHS) of the CC in contact therewith, in which respective lengths along that CHS of high- and low-resistance regions is variable in write mode, and a gate terminal provided on that CHS for controlling resistance of the CHS in response to control signal(s) (CS) applied to the gate terminal; and circuitry configured to apply the CS such that, in read mode, a RME(s) is selected by applying a CS producing CHS with resistance between the resistance regions of the RMM; and remaining RME(s) are deselected by applying CS producing CHS having resistance less than the low-resistance region.
    Type: Grant
    Filed: May 4, 2018
    Date of Patent: August 27, 2019
    Assignee: International Business Machines Corporation
    Inventors: Lukas Czornomaz, Veeresh Vidyadhar Deshpande, Vara Sudananda Prasad Jonnalagadda, Wabe Koelmans, Abu Sebastian
  • Publication number: 20180254083
    Abstract: Apparatus including: memory cell unit(s) having a variable-resistance channel component (CC) extending between first and second supply terminals for supplying read and write (R/W) signals to the unit in respective R/W modes, and resistive memory elements (RMEs) arranged along the CC, RME includes resistive memory material (RMM), extending along a respective channel segment (CHS) of the CC in contact therewith, in which respective lengths along that CHS of high- and low-resistance regions is variable in write mode, and a gate terminal provided on that CHS for controlling resistance of the CHS in response to control signal(s) (CS) applied to the gate terminal; and circuitry configured to apply the CS such that, in read mode, a RME(s) is selected by applying a CS producing CHS with resistance between the resistance regions of the RMM; and remaining RME(s) are deselected by applying CS producing CHS having resistance less than the low-resistance region.
    Type: Application
    Filed: May 4, 2018
    Publication date: September 6, 2018
    Inventors: Lukas Czornomaz, Veeresh Vidyadhar Deshpande, Vara Sudananda Prasad Jonnalagadda, Wabe Koelmans, Abu Sebastian
  • Patent number: 10037800
    Abstract: Apparatus including: memory cell unit(s) having a variable-resistance channel component (CC) extending between first and second supply terminals for supplying read and write (R/W) signals to the unit in respective R/W modes, and resistive memory elements (RMEs) arranged along the CC, RME includes resistive memory material (RMM), extending along a respective channel segment (CHS) of the CC in contact therewith, in which respective lengths along that CHS of high- and low-resistance regions is variable in write mode, and a gate terminal provided on that CHS for controlling resistance of the CHS in response to control signal(s) (CS) applied to the gate terminal; and circuitry configured to apply the CS such that, in read mode, a RME(s) is selected by applying a CS producing CHS with resistance between the resistance regions of the RMM; and remaining RME(s) are deselected by applying CS producing CHS having resistance less than the low-resistance region.
    Type: Grant
    Filed: September 28, 2016
    Date of Patent: July 31, 2018
    Assignee: International Business Machines Corporation
    Inventors: Lukas Czornomaz, Veeresh Vidyadhar Deshpande, Vara Sudananda Prasad Jonnalagadda, Wabe Koelmans, Abu Sebastian
  • Publication number: 20180090203
    Abstract: Apparatus including: memory cell unit(s) having a variable-resistance channel component (CC) extending between first and second supply terminals for supplying read and write (R/W) signals to the unit in respective R/W modes, and resistive memory elements (RMEs) arranged along the CC, RME includes resistive memory material (RMM), extending along a respective channel segment (CHS) of the CC in contact therewith, in which respective lengths along that CHS of high- and low-resistance regions is variable in write mode, and a gate terminal provided on that CHS for controlling resistance of the CHS in response to control signal(s) (CS) applied to the gate terminal; and circuitry configured to apply the CS such that, in read mode, a RME(s) is selected by applying a CS producing CHS with resistance between the resistance regions of the RMM; and remaining RME(s) are deselected by applying CS producing CHS having resistance less than the low-resistance region.
    Type: Application
    Filed: September 28, 2016
    Publication date: March 29, 2018
    Inventors: Lukas Czornomaz, Veeresh Vidyadhar Deshpande, Vara Sudanan Prasad Jonnalagadda, Wabe Koelmans, Abu Sebastian
  • Publication number: 20170171102
    Abstract: Systems and methods for building service templates that allow for an agentless, data-driven and stateful automation of a provisioning of services to mobile network customers. Data associated with a request to create a target schema object class for a device and protocol are received. Based on the device and protocol information, a set of data fields associated with CRUD semantics is retrieved from either a database or from user provided data. A decorated target object class is created based on the requested target schema object class. A subrecipe is created including the decorated target object class, and one or more other decorated target object classes. A recipe is processed for transmission to an execution engine to form a service instance, the service instance being customizable by an operator for a specific network device such that the service instance data fields that are not pre-filled can be customized by the operator.
    Type: Application
    Filed: December 9, 2016
    Publication date: June 15, 2017
    Inventors: Ronald M. PARKER, Prasad JONNALAGADDA
  • Patent number: 9570169
    Abstract: A memory device includes a plurality of memory cells and a control unit. The memory cells include a first segment including a resistive memory material for storing information in a plurality of resistance states, a second segment including a non-insulating material, a first terminal, a second terminal, and a third terminal. The first segment and the second segment are arranged in parallel between the first terminal and the second terminal. The control unit is configured to apply in a write mode a write voltage to the first and the second terminal for writing the resistance state, and to apply in a read mode a read voltage to the first and the second terminal for reading the resistance state, and to apply a control signal to the third terminal for adjusting the electrical resistance of the second segment. A related method and control unit are also disclosed.
    Type: Grant
    Filed: June 3, 2016
    Date of Patent: February 14, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Lukas Czornomaz, Veeresh V. Deshpande, Vara Sudananda Prasad Jonnalagadda, Wabe Koelmans, Abu Sebastian
  • Publication number: 20150194173
    Abstract: A tape head, adapted for reading and/or writing to a magnetic tape, has a tape-bearing surface and is configured to urge a magnetic tape against the bearing surface, in operation. The bearing surface includes a transducer area, having at least one transducer that is a read and/or write element, designed for reading and/or writing to a magnetic tape, and a structured area adjacent to the transducer area, comprising a periodic array of topographic features, the topographic features configured within the structured area to determine a minimal distance between the transducer area and a tape.
    Type: Application
    Filed: March 24, 2015
    Publication date: July 9, 2015
    Inventors: Laurent A. Dellmann, Johan B.C. Engelen, Vara Sudananda Prasad Jonnalagadda, Mark A. Lantz
  • Patent number: 9030779
    Abstract: A tape head, adapted for reading and/or writing to a magnetic tape, has a tape-bearing surface and is configured to urge a magnetic tape against the bearing surface, in operation. The bearing surface includes a transducer area, having at least one transducer that is a read and/or write element, designed for reading and/or writing to a magnetic tape, and a structured area adjacent to the transducer area, comprising a periodic array of topographic features, the topographic features configured within the structured area to determine a minimal distance between the transducer area and a tape.
    Type: Grant
    Filed: June 4, 2014
    Date of Patent: May 12, 2015
    Assignee: International Business Machines Corporation
    Inventors: Laurent A. Dellmann, Johan B. C. Engelen, Vara Sudananda Prasad Jonnalagadda, Mark A. Lantz
  • Publication number: 20140368953
    Abstract: A tape head, adapted for reading and/or writing to a magnetic tape, has a tape-bearing surface and is configured to urge a magnetic tape against the bearing surface, in operation. The bearing surface includes a transducer area, having at least one transducer that is a read and/or write element, designed for reading and/or writing to a magnetic tape, and a structured area adjacent to the transducer area, comprising a periodic array of topographic features, the topographic features configured within the structured area to determine a minimal distance between the transducer area and a tape.
    Type: Application
    Filed: June 4, 2014
    Publication date: December 18, 2014
    Applicant: International Business Machines Corporation
    Inventors: Laurent A. Dellmann, Johan B.C. Engelen, Vara Sudananda Prasad Jonnalagadda, Mark A. Lantz
  • Publication number: 20080232590
    Abstract: A method of producing an offer package includes defining, within the offer package, a description of an offered product. The cost of the offered product and the merchant making the offer are also defined within the offer package, which includes an encrypted version of the offered product.
    Type: Application
    Filed: January 23, 2004
    Publication date: September 25, 2008
    Inventors: Ronald L. Rivest, Silvio Micali, Perry Solomon, Robert Nix, Robert Carney, Prasad Jonnalagadda, Joseph Bergeron III, Mark Bates
  • Publication number: 20060149671
    Abstract: A payment processing system includes one transaction processor that aggregates cost data associated with low-priced sales transactions between a consumer and a merchant. The transaction processor sends data that represents the aggregated cost data to an acquiring banking entity associated with the merchant. The system also includes another transaction processor that stores data that represents each individual low-priced sales transaction. The stored data is accessible by one or more banking entities associated with the merchant.
    Type: Application
    Filed: June 27, 2005
    Publication date: July 6, 2006
    Inventors: Robert Nix, Alek Mesarovich, Theodore Schwartz, Jeffrey Schachter, Peter Masters, Jason Mondanaro, Ronald Rivest, Silvio Micali, Prasad Jonnalagadda