Patents by Inventor Prasad Kotra

Prasad Kotra has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230288979
    Abstract: Apparatuses and methods of operating a flexible and optimized power management unit (PMU) for multiple power supply scenarios are described. One integrated circuit includes a first terminal to couple to an unregulated power supply, a second terminal to couple to a regulated power supply, a first regulator, and a second regulator. The first regulator outputs a first supply voltage in a first configuration, and the second regulator outputs a second supply voltage in a second configuration. The first and second regulators do not operate concurrently.
    Type: Application
    Filed: March 8, 2022
    Publication date: September 14, 2023
    Applicant: Cypress Semiconductor Corporation
    Inventors: Radhika VENKATASUBRAMANIAN, Stephen DOW, Prasad KOTRA, Victor SIMILEYSKY, Ataur Rehman KHAN, David MOELLER, Brian BALLWEBER
  • Patent number: 7612585
    Abstract: An input buffer has a high voltage leg in parallel with a low voltage leg. The low voltage leg pulls up the pad when the pad voltage is below the power supply voltage. The high voltage leg remains off when the pad voltage is below the power supply. The low voltage leg is turned off when the pad voltage is above the power supply voltage. The high voltage leg is on when the pad voltage is above power supply voltage. A low voltage bias circuit and a high voltage bias circuit protect the transistors in the low and voltage legs when the pad voltage is above the power supply voltage. As a result, the pull-up circuit is high voltage tolerant and does not sink the current from pad.
    Type: Grant
    Filed: January 17, 2007
    Date of Patent: November 3, 2009
    Assignee: Cypress Semiconductor Corporation
    Inventors: Pulkit Shah, Prasad Kotra
  • Publication number: 20070164804
    Abstract: An input buffer has a high voltage leg in parallel with a low voltage leg. The low voltage leg pulls up the pad when the pad voltage is below the power supply voltage. The high voltage leg remains off when the pad voltage is below the power supply. The low voltage leg is turned off when the pad voltage is above the power supply voltage. The high voltage leg is on when the pad voltage is above power supply voltage. A low voltage bias circuit and a high voltage bias circuit protect the transistors in the low and voltage legs when the pad voltage is above the power supply voltage. As a result, the pull-up circuit is high voltage tolerant and does not sink the current from pad.
    Type: Application
    Filed: January 17, 2007
    Publication date: July 19, 2007
    Inventors: Pulkit Shah, Prasad Kotra
  • Patent number: 7221200
    Abstract: A programmable low voltage reset apparatus for a device having a plurality of power supplies comprises a low voltage signal generator for sensing when a power supply output decreases below a predetermined voltage and generating a reset signal, a reset selector for selecting one of the power supplies, and a programmable reference voltage for varying a reference voltage according to the voltage of the selected power supply.
    Type: Grant
    Filed: March 8, 2005
    Date of Patent: May 22, 2007
    Assignee: Cypress Semiconductor Corp.
    Inventors: Prasad Kotra, Sunil Thamaran, Shailesh Shah