Abstract: The clock signal supplied to the delta-sigma modulator in a fractional-N phase-locked loop is dithered. In one example, the PLL includes a novel programmable clock dithering circuit. The programmable clock dithering circuit is controllable via a serial bus to dither the phase of the clock signal in a selected one of several ways. If the clock signal is dithered in a first way (pseudo-random phase dithering), then the power of digital noise generated by the delta-sigma modulator is spread over a frequency band, thereby reducing the degree to which the noise interferes with other circuitry. If the clock signal is dithered in a second way (rotational phase dithering), then the power of digital noise is frequency shifted such that the degree to which the noise interferes with the other circuitry is reduced. The programmable clock dithering circuit can be controlled in other ways. For example, dithering can be programmably disabled.

Abstract: Techniques for attenuating undesired signal components from a differential duplexer are described. The duplexer provides a differential received signal at RX+ and RX? ports. This differential received signal includes an undesired common mode signal, which may come from a transmit signal. The common mode signal is attenuated with a common mode trap in an impedance matching network coupled to the RX+ and RX? ports. The matching network includes a first passive circuit coupled between the RX+ port and a first node, a second passive circuit coupled between the RX? port and a second node, and the common mode trap coupled between the first and second nodes. In one design, the common mode trap includes a first inductor coupled between the first node and a common node, a second inductor coupled between the second node and the common node, and a capacitor coupled between the common node and circuit ground.

Abstract: Techniques for generating local oscillator (LO) signals are described. In one design, an apparatus may include a deskew circuit and a divider circuit. The deskew circuit may receive a differential input oscillator signal having timing skew and provide a differential output oscillator signal having reduced timing skew. The differential input oscillator signal may include first and second input oscillator signals, and the differential output oscillator signal may include first and second output oscillator signals. In one design, the deskew circuit may include first and second variable delay circuits that receive the first and second input oscillator signals, respectively, and provide the first and second output oscillator signals, respectively. Each output oscillator signal may have an adjustable delay selected to reduce timing skew. The divider circuit may divide the differential output oscillator signal in frequency and provide differential I and Q divided signals, which may be used to generate LO signals.

Abstract: A receiver includes a low noise amplifier (LNA) and multiple pairs of mixers. The LNA receives and amplifies an LNA input signal and provides at least one LNA output signal. Each pair of mixers downconverts one of the at least one LNA output signal when enabled. Each pair of mixers may be selectively enabled or disabled, e.g., based on a mode selected from among multiple modes. In one design, the LNA includes multiple load sections coupled in parallel. Each load section may be selectively enabled or disabled, e.g., based on the selected mode. In one design, first and second pairs of mixers and first and second load sections may be enabled for a high linearity mode. The first pair of mixers and the first load section may be enabled and the second pair of mixers and the second load section may be disabled for a low linearity mode.

Abstract: An electronic device includes an amplifier circuit coupled to a linearizer. The amplifier circuit may receive a first input signal including first and second frequencies and generate a first output signal including a delta frequency signal at a delta frequency, which is the difference between the first frequency and the second frequency. The linearizer includes a signal detector circuit, a current-mirror circuit, a low pass filter, a phase shifter, and a bias circuit. The signal detector circuit may generate a second output signal. The current-mirror circuit may adjust an amplitude of a signal. The low pass filter may eliminate a portion of the second output signal having frequencies greater than the delta frequency. The phase shifter may generate a feedback signal corresponding to the delta frequency signal. An amplitude and/or a phase of the feedback signal is different from an amplitude and/or a phase of the delta frequency signal.

Abstract: An integrated circuit for achieving power reduction in a transceiver may include a jammer detector that determines an interference level corresponding to a received signal, and a transmit power detector that determines a required transmit power level for a transmitted signal. The integrated circuit may also include at least one of the following: a process monitor that determines process corners of components within the receiver and/or the transmitter, and a temperature monitor that determines a temperature of the receiver and/or the transmitter. The integrated circuit may also include a state machine. The state machine may transition the receiver from a high linearity mode to a low linearity mode if a set of operating conditions is satisfied. Similarly, the state machine may transition the transmitter from a high power mode to a low power mode if a set of operating conditions is satisfied.

Abstract: A receiver includes a jammer detector configured to detect the presence or the absence of jamming in a communication signal within a gain state. The receiver further includes an amplifier configured to amplify the communication signal in a high linearity receiving mode or a low linearity receiving mode, wherein the high linearity receiving mode corresponds with a lower gain for the gain state in the amplifier relative to that of the low linearity receiving mode. In addition, the receiver includes a processing unit coupled to the jammer detector, the processing unit being configured to control the amplifier to amplify the communication signal in either the high linearity receiving mode or the low linearity receiving mode, based on the output of the jammer detector detecting the presence or the absence of jamming in the communication signal. A method is also provided for processing a communication signal in a receiver.

Abstract: A communication channel has a highly linear switched current mixer that incorporates passive filtering (e.g., low pass, notch) for improved transmitting (Tx) and receiving (Rx) with adding external filtering components. A high IIP2 (input referenced second order intercept point) of the receiver at the Tx offset is essential to avoid corrupting the system's sensitivity performance, and a high triple beat (TB) is required to avoid sensitivity degradation due to transmitter leakage. Thanks to the embedded filtering in the mixer and the active post-distortion (APD) method in a low noise amplifier (LNA), the required high linearity is achieved with low noise figure and power consumption, overcoming transmitter power leakage without the use of a SAW (surface acoustic wave) filter.

Abstract: The clock signal supplied to the delta-sigma modulator in a fractional-N phase-locked loop is dithered. In one example, the PLL includes a novel programmable clock dithering circuit. The programmable clock dithering circuit is controllable via a serial bus to dither the phase of the clock signal in a selected one of several ways. If the clock signal is dithered in a first way (pseudo-random phase dithering), then the power of digital noise generated by the delta-sigma modulator is spread over a frequency band, thereby reducing the degree to which the noise interferes with other circuitry. If the clock signal is dithered in a second way (rotational phase dithering), then the power of digital noise is frequency shifted such that the degree to which the noise interferes with the other circuitry is reduced. The programmable clock dithering circuit can be controlled in other ways. For example, dithering can be programmably disabled.

Abstract: An electronic device includes an amplifier circuit coupled to a linearizer. The amplifier circuit may receive a first input signal including first and second frequencies and generate a first output signal including a delta frequency signal at a delta frequency, which is the difference between the first frequency and the second frequency. The linearizer includes a signal detector circuit, a current-mirror circuit, a low pass filter, a phase shifter, and a bias circuit. The signal detector circuit may generate a second output signal. The current-mirror circuit may adjust an amplitude of a signal. The low pass filter may eliminate a portion of the second output signal having frequencies greater than the delta frequency. The phase shifter may generate a feedback signal corresponding to the delta frequency signal. An amplitude and/or a phase of the feedback signal is different from an amplitude and/or a phase of the delta frequency signal.

Abstract: An adaptive bias method and circuits for amplifiers that provide a substantial current boost based at least partly upon a sensed input power of an amplifier circuit. Methods and circuits of the invention provide an additional bias current based upon the sensed input power. Circuits of the invention may be simple, area-efficient, low-power, stable and digitally-programmable. In addition, methods and circuits of the invention may be used with a number of amplifier circuit configurations, including amplifiers having either inductor and/or resistive degeneration.

Abstract: A differential low noise amplifier (LNA) involves two main amplifying transistors biased in saturation, and two cancel transistors biased in sub-threshold. In one example, the gates of the cancel transistors are coupled to the drains of main transistors, in a symmetrical and cross-coupled fashion. The main transistors are source degenerated. Because the gates of cancel transistors are not coupled to the differential input leads of the LNA, the input capacitance of the LNA is reduced. Noise introduced into the LNA output due to the cancel transistors being biased in the sub-threshold region is reduced because there are two stages. The first stage involves the main transistors, and the second stage involves the cancel transistors. By increasing the gain of the first stage and decreasing the gain of the second stage, overall LNA gain is maintained while reducing the noise that the sub-threshold biased transistors contribute to the LNA output.

Abstract: Sub-carrier selection methods and receiver architectures for receiving an Orthogonal Frequency Division Multiplexing band sensed by a plurality of antennas (101-10N). Filtering is applied to separately pass portions of the predetermined Orthogonal Division Multiplexing frequency band. Each separate portion encompasses one or more sub-bands of the predetermined Orthogonal Division Multiplexing frequency band. For each of the separate portions of the predetermined Orthogonal Division Multiplexing frequency band, the signal received from one of the plurality of antennas is selected. The selected signals for each separate portion are then combined in the time (analog) domain.

Abstract: Techniques for attenuating undesired signal components from a differential duplexer are described. The duplexer provides a differential received signal at RX+ and RX? ports. This differential received signal includes an undesired common mode signal, which may come from a transmit signal. The common mode signal is attenuated with a common mode trap in an impedance matching network coupled to the RX+ and RX? ports. The matching network includes a first passive circuit coupled between the RX+ port and a first node, a second passive circuit coupled between the RX? port and a second node, and the common mode trap coupled between the first and second nodes. In one design, the common mode trap includes a first inductor coupled between the first node and a common node, a second inductor coupled between the second node and the common node, and a capacitor coupled between the common node and circuit ground.

Abstract: Active circuits with active loads linearized via distortion cancellation are described. In one design, an apparatus includes a first stage and a load stage. For an amplifier, the first stage amplifies an input signal and provides an output signal having a larger signal level. For a mixer, the first stage mixes an input signal with an LO signal and provides an output signal. The load stage provides an active load for the first stage and is linearized by canceling distortion generated by the active load. In one design, the load stage includes a first transistor that provides the active load and generates distortion due to its nonlinearity. The load stage further includes at least one transistor that generates a replica of the distortion from the first transistor. The distortion replica is used to cancel the distortion from the first transistor. The first stage may also be linearized with distortion cancellation.

Abstract: An apparatus, which may be configured as a receiver or transceiver, includes a plurality of super regenerative (SR) amplifiers coupled in parallel, wherein the SR amplifiers are tuned to distinct frequency bands, respectively. The apparatus may further include isolation amplifiers at the respective inputs and outputs of the SR amplifiers to prevent injection locking and reduce power leakage. The apparatus may include a circuit to reduce or substantially eliminate in-band jamming signals. The apparatus may form at least part of a wireless communications device adapted to receive signals from other wireless communications devices, adapted to transmit signal to other wireless communications devices, and adapted to both transmit and receive signals to and from other wireless communications devices.

Abstract: This disclosure describes techniques for reducing adverse effects of TX signal leakage in a full-duplex, wireless communication device. The techniques make use of a notch filter to reject TX signal leakage in a signal processed in the RX path of the wireless communication device. The notch filter may be constructed as a complex notch filter using passive resistor and capacitor components to produce a notch frequency that attenuates TX signal leakage components in a desired signal. The notch filter may be applied to a down-converted, baseband signal produced by a passive mixer.