Abstract: A peak current controlled switching voltage regulator system and method for providing a self-power down mode. An on-chip voltage regulator integrated into an on-chip digital logic circuit provides a core supply voltage to the on-chip digital logic circuit along with an off-chip inductor. An off-chip regulator connected to the on-chip digital logic circuit provides an external core supply voltage with respect to the on-chip digital logic circuit. A start-up circuit operates the on-chip voltage regulator in a self-power down mode for a pre-determined time period when the on-chip regulator is not connected to the off-chip inductor in order to maintain an equilibrium voltage supply with respect to the on-chip digital logic circuit.

Abstract: A system and method for controlling ripple in an output voltage of a switching regulator is described. In one embodiment, the method includes providing a ramp circuit to selectively charge and discharge a ramp capacitor. The ramp capacitor provides a ramp voltage. The ramp voltage is selectively added to the output voltage to generate a summation voltage. The summation voltage is compared to a reference voltage to generate a control signal. An input voltage is coupled to an LC circuit based on the control signal. The LC circuit provides the output voltage. The input voltage is selectively coupled to the LC circuit when the ramp capacitor is selectively charged.

Abstract: An apparatus comprising a reference circuit, a resistor ladder, and an output circuit. The reference circuit may be configured to generate a reference signal in response to (i) a clock signal, (ii) a first phase signal and (iii) a second phase signal. The resistor ladder circuit may be configured to generate a tap voltage in response to the reference signal. The tap voltage may be generated by enabling one or more of a plurality of tap resistors. The output circuit may be configured to generate an adjusted clock signal in response to (i) the tap voltage, (ii) the clock signal, (iii) the first phase signal, (iv) the second phase signal, and (v) a reset signal. The adjusted clock signal may have an adjusted phase with respect to the clock signal.

Abstract: A switching voltage regulator system and method for providing a start-up mode. An on-chip voltage regulator can be integrated with an on-chip digital logic circuit to provide a core supply voltage to the on-chip digital logic circuit along with an off-chip inductor and capacitor. A clock less start-up circuit automatically operates the on-chip voltage regulator in a start-up mode in order to maintain an equilibrium voltage supply with respect to the on-chip digital logic circuit. Such clock less start-up circuit provides soft start-up operation with respect to the on-chip voltage regulator without a clock signal.

Abstract: A circuit includes a PMOS body bias circuit including a PMOS charge pump for generating a positive supply voltage, a PMOS reference voltage generator for providing a PMOS reference voltage, and a PMOS linear voltage regulator circuit for generating a PMOS body bias voltage upon receiving the positive supply voltage and the PMOS reference voltage. The circuit also includes a NMOS body bias circuit including a NMOS charge pump for generating a negative supply voltage, a NMOS reference voltage generator for providing a NMOS reference voltage, and a NMOS linear voltage regulator circuit for generating a NMOS body bias voltage upon receiving the negative supply voltage and the NMOS reference voltage. The PMOS body bias voltage and the NMOS body bias voltage drive bulk of PMOS and NMOS devices in the integrated circuit.

Abstract: An apparatus comprising a reference circuit, a resistor ladder, and an output circuit. The reference circuit may be configured to generate a reference signal in response to (i) a clock signal, (ii) a first phase signal and (iii) a second phase signal. The resistor ladder circuit may be configured to generate a tap voltage in response to the reference signal. The tap voltage may be generated by enabling one or more of a plurality of tap resistors. The output circuit may be configured to generate an adjusted clock signal in response to (i) the tap voltage, (ii) the clock signal, (iii) the first phase signal, (iv) the second phase signal, and (v) a reset signal. The adjusted clock signal may have an adjusted phase with respect to the clock signal.

Abstract: A system and method for controlling ripple in an output voltage of a switching regulator is described. In one embodiment, the method includes providing a ramp circuit to selectively charge and discharge a ramp capacitor. The ramp capacitor provides a ramp voltage. The ramp voltage is selectively added to the output voltage to generate a summation voltage. The summation voltage is compared to a reference voltage to generate a control signal. An input voltage is coupled to an LC circuit based on the control signal. The LC circuit provides the output voltage. The input voltage is selectively coupled to the LC circuit when the ramp capacitor is selectively charged.

Abstract: A switching voltage regulator system and method for providing a start-up mode. An on-chip voltage regulator can be integrated with an on-chip digital logic circuit to provide a core supply voltage to the on-chip digital logic circuit along with an off-chip inductor and capacitor. A clock less start-up circuit automatically operates the on-chip voltage regulator in a start-up mode in order to maintain an equilibrium voltage supply with respect to the on-chip digital logic circuit. Such clock less start-up circuit provides soft start-up operation with respect to the on-chip voltage regulator without a clock signal.

Abstract: A peak current controlled switching voltage regulator system and method for providing a self-power down mode. An on-chip voltage regulator integrated into an on-chip digital logic circuit provides a core supply voltage to the on-chip digital logic circuit along with an off-chip inductor. An off-chip regulator connected to the on-chip digital logic circuit provides an external core supply voltage with respect to the on-chip digital logic circuit. A start-up circuit operates the on-chip voltage regulator in a self-power down mode for a predetermined time period when the on-chip regulator is not connected to the off-chip inductor in order to maintain an equilibrium voltage supply with respect to the on-chip digital logic circuit.

Abstract: A circuit and method for generating body bias voltage for an integrated circuit is disclosed. The circuit includes a PMOS body bias circuit including a PMOS charge pump for generating a positive supply voltage, a PMOS reference voltage generator for providing a PMOS reference voltage, and a PMOS linear voltage regulator circuit for generating a PMOS body bias voltage upon receiving the positive supply voltage and the PMOS reference voltage. The circuit also includes a NMOS body bias circuit including a NMOS charge pump for generating a negative supply voltage, a NMOS reference voltage generator for providing a NMOS reference voltage, and a NMOS linear voltage regulator circuit for generating a NMOS body bias voltage upon receiving the negative supply voltage and the NMOS reference voltage. The PMOS body bias voltage and the NMOS body bias voltage drive bulk of PMOS and NMOS devices in the integrated circuit.