Patents by Inventor Prasad Subramaniam
Prasad Subramaniam has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11977580Abstract: Methods, systems, and computer program products for partitioning and parallel loading of property graphs with constraints are provided herein. A computer-implemented method includes obtaining graph-related input data and corresponding constraint data, wherein the graph-related input data and corresponding constraint data are at least one of user-defined and input data model-based; generating at least one in-memory graph based at least in part on processing at least a portion of the obtained graph-related input data; partitioning the at least one in-memory graph into two or more sub-graphs by processing the at least one in-memory graph using one or more polynomial time partition algorithms; and generating at least one property graph by allocating, at least a portion of the two or more partitioned sub-graphs which satisfy the obtained constraint data, to two or more threads that run in parallel.Type: GrantFiled: November 30, 2021Date of Patent: May 7, 2024Assignee: International Business Machines CorporationInventors: Sumit Neelam, Hima Prasad Karanam, Udit Sharma, Shajith Ikbal Mohamed, Santosh Srivastava, L. Venkata Subramaniam
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Patent number: 11942409Abstract: An integrated circuit includes a first set of dies, each die comprising circuitry and a second set of interposer dies. At least two dies of the first set of dies are connected to each other via at least one of the interposer dies. The at least one of the interposer dies includes first connections connected to a first die of the first set of dies, second connections connected to a second die of the first set of dies, and buffers connected between the first connections and the second connections. The buffers are configured to condition signals between the first die and the second die.Type: GrantFiled: January 24, 2022Date of Patent: March 26, 2024Assignee: MARVELL ASIA PTE LTDInventors: Ferran Martorell, Prasad Subramaniam
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Publication number: 20220148957Abstract: An integrated circuit includes a first set of dies, each die comprising circuitry and a second set of interposer dies. At least two dies of the first set of dies are connected to each other via at least one of the interposer dies. The at least one of the interposer dies includes first connections connected to a first die of the first set of dies, second connections connected to a second die of the first set of dies, and buffers connected between the first connections and the second connections. The buffers are configured to condition signals between the first die and the second die.Type: ApplicationFiled: January 24, 2022Publication date: May 12, 2022Inventors: Ferran MARTORELL, Prasad SUBRAMANIAM
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Patent number: 11233002Abstract: An electronic circuit is implementing using a first logic die, a second logic die, and an interposer array connecting the first logic die to the second logic die. The first logic die includes an array of output contacts. The second logic die includes an array of input contacts. The interposer array includes a plurality of interposer dice. Each interposer die includes a plurality of input contacts and a plurality of output contacts. The array of output contacts of the first logic die is bonded to at least a subset of input contacts from the plurality of input contacts of an interposer die of the plurality of interposer dice. The array of input contacts of the second logic die is bonded to at least a subset of output contacts from the plurality of output contacts of the interposer die of the plurality of interposer dice.Type: GrantFiled: January 21, 2020Date of Patent: January 25, 2022Assignee: MARVELL ASIA PTE, LTD.Inventors: Ferran Martorell, Prasad Subramaniam
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Publication number: 20210111113Abstract: An electronic circuit is implementing using a first logic die, a second logic die, and an interposer array connecting the first logic die to the second logic die. The first logic die includes an array of output contacts. The second logic die includes an array of input contacts. The interposer array includes a plurality of interposer dice. Each interposer die includes a plurality of input contacts and a plurality of output contacts. The array of output contacts of the first logic die is bonded to at least a subset of input contacts from the plurality of input contacts of an interposer die of the plurality of interposer dice. The array of input contacts of the second logic die is bonded to at least a subset of output contacts from the plurality of output contacts of the interposer die of the plurality of interposer dice.Type: ApplicationFiled: January 21, 2020Publication date: April 15, 2021Inventors: Ferran Martorell, Prasad Subramaniam
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Patent number: 9943606Abstract: Dendritic polypeptides useful for the delivery of therapeutic agents into cells are disclosed, together with their methods of preparation. These dendritic polypeptides serve as carriers of drugs, siRNA, aptamers and plasmid DNA in the treatment of various diseases, including cancer.Type: GrantFiled: January 12, 2015Date of Patent: April 17, 2018Assignee: RUTGERS, THE STATE UNIVERSITY OF NEW JERSEYInventors: Ki-Bum Lee, Prasad Subramaniam, Dipti N. Barman
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Patent number: 9852250Abstract: Memory optimization of integrated circuit (IC) design using generic memory models is presented. One method includes accessing a register transfer level (RTL) description for the IC design that includes generic memory interface calls to generic memory models for each memory instance. The generic memory call interface includes a set of memory parameters. The method also includes processing the RTL description of the IC design as a step in a design flow for the IC design by processing specific memory models for the memory instances, wherein the specific memory model for each memory instance is generated from the generic memory model using the memory parameters corresponding to the memory instance. The method can also include generating specific memory models (e.g., simulation model, timing model, and layout model) for each memory instance based on a given set of values of memory parameters for the memory instance.Type: GrantFiled: February 20, 2015Date of Patent: December 26, 2017Assignee: eSilicon CorporationInventors: Prasad Subramaniam, Hai Phuong
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Patent number: 9727681Abstract: Memory optimization of integrated circuit (IC) design using generic memory models is presented. One method includes accessing a register transfer level (RTL) description for the IC design that includes generic memory interface calls to generic memory models for each memory instance. The generic memory call interface includes a set of memory parameters. The method also includes processing the RTL description of the IC design as a step in a design flow for the IC design by processing specific memory models for the memory instances, wherein the specific memory model for each memory instance is generated from the generic memory model using the memory parameters corresponding to the memory instance. The method can also include generating specific memory models (e.g., simulation model, timing model, and layout model) for each memory instance based on a given set of values of memory parameters for the memory instance.Type: GrantFiled: February 23, 2015Date of Patent: August 8, 2017Assignee: eSilicon CorporationInventors: Prasad Subramaniam, Hai Phuong
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Patent number: 9727682Abstract: Memory optimization of integrated circuit (IC) design using generic memory models is presented. One method includes accessing a register transfer level (RTL) description for the IC design that includes generic memory interface calls to generic memory models for each memory instance. The generic memory call interface includes a set of memory parameters. The method also includes processing the RTL description of the IC design as a step in a design flow for the IC design by processing specific memory models for the memory instances, wherein the specific memory model for each memory instance is generated from the generic memory model using the memory parameters corresponding to the memory instance. The method can also include generating specific memory models (e.g., simulation model, timing model, and layout model) for each memory instance based on a given set of values of memory parameters for the memory instance.Type: GrantFiled: February 23, 2015Date of Patent: August 8, 2017Assignee: eSilicon CorporationInventors: Prasad Subramaniam, Hai Phuong
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Publication number: 20160371411Abstract: In one aspect, a method for providing design point recommendations for an integrated circuit (IC) design is disclosed. The method comprises receiving an IC design along with a reference PPA (power, performance, area) metric at a reference design point, and a target PPA metric. The method also comprises estimating trial PPA metrics for the IC design at multiple design points, wherein estimating trial PPA metric at each design point includes accessing a PPA database containing PPA metrics for multiple test components, determining scale factors from the reference design point to the trial design point for test components equivalent to components of the IC design, and applying the scale factors to the reference PPA metric to determine the trial PPA metric for the trial design point. The method further comprises recommending a trial design point based on the estimated trial PPA metric and the received target PPA metric.Type: ApplicationFiled: August 29, 2016Publication date: December 22, 2016Inventors: Prasad Subramaniam, Hao Nham, Rakesh Chadha, Ferran Martorell
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Publication number: 20160292313Abstract: In one aspect, a method for providing design point recommendations for an integrated circuit (IC) design is disclosed. The method comprises receiving an IC design along with a reference PPA (power, performance, area) metric at a reference design point, and a target PPA metric. The method also comprises estimating trial PPA metrics for the IC design at multiple design points, wherein estimating trial PPA metric at each design point includes accessing a PPA database containing PPA metrics for multiple test components, determining scale factors from the reference design point to the trial design point for test components equivalent to components of the IC design, and applying the scale factors to the reference PPA metric to determine the trial PPA metric for the trial design point. The method further comprises recommending a trial design point based on the estimated trial PPA metric and the received target PPA metric.Type: ApplicationFiled: April 3, 2015Publication date: October 6, 2016Inventors: Prasad Subramaniam, Hao Nham, Rakesh Chadha, Ferran Martorell
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Publication number: 20160292315Abstract: In one aspect, a method for providing design point recommendations for an integrated circuit (IC) design is disclosed. The method comprises receiving an IC design along with a reference PPA (power, performance, area) metric at a reference design point, and a target PPA metric. The method also comprises estimating trial PPA metrics for the IC design at multiple design points, wherein estimating trial PPA metric at each design point includes accessing a PPA database containing PPA metrics for multiple test components, determining scale factors from the reference design point to the trial design point for test components equivalent to components of the IC design, and applying the scale factors to the reference PPA metric to determine the trial PPA metric for the trial design point. The method further comprises recommending a trial design point based on the estimated trial PPA metric and the received target PPA metric.Type: ApplicationFiled: April 3, 2015Publication date: October 6, 2016Inventors: Prasad Subramaniam, Hao Nham, Rakesh Chadha, Ferran Martorell
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Publication number: 20160292316Abstract: In one aspect, a method for providing design point recommendations for an integrated circuit (IC) design is disclosed. The method comprises receiving an IC design along with a reference PPA (power, performance, area) metric at a reference design point, and a target PPA metric. The method also comprises estimating trial PPA metrics for the IC design at multiple design points, wherein estimating trial PPA metric at each design point includes accessing a PPA database containing PPA metrics for multiple test components, determining scale factors from the reference design point to the trial design point for test components equivalent to components of the IC design, and applying the scale factors to the reference PPA metric to determine the trial PPA metric for the trial design point. The method further comprises recommending a trial design point based on the estimated trial PPA metric and the received target PPA metric.Type: ApplicationFiled: April 3, 2015Publication date: October 6, 2016Inventors: Prasad Subramaniam, Hao Nham, Rakesh Chadha, Ferran Martorell
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Publication number: 20160292343Abstract: In one aspect, a method for providing design point recommendations for an integrated circuit (IC) design is disclosed. The method comprises receiving an IC design along with a reference PPA (power, performance, area) metric at a reference design point, and a target PPA metric. The method also comprises estimating trial PPA metrics for the IC design at multiple design points, wherein estimating trial PPA metric at each design point includes accessing a PPA database containing PPA metrics for multiple test components, determining scale factors from the reference design point to the trial design point for test components equivalent to components of the IC design, and applying the scale factors to the reference PPA metric to determine the trial PPA metric for the trial design point. The method further comprises recommending a trial design point based on the estimated trial PPA metric and the received target PPA metric.Type: ApplicationFiled: April 2, 2015Publication date: October 6, 2016Inventors: Prasad Subramaniam, Hao Nham, Rakesh Chadha, Ferran Martorell
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Publication number: 20160292317Abstract: In one aspect, a method for providing design point recommendations for an integrated circuit (IC) design is disclosed. The method comprises receiving an IC design along with a reference PPA (power, performance, area) metric at a reference design point, and a target PPA metric. The method also comprises estimating trial PPA metrics for the IC design at multiple design points, wherein estimating trial PPA metric at each design point includes accessing a PPA database containing PPA metrics for multiple test components, determining scale factors from the reference design point to the trial design point for test components equivalent to components of the IC design, and applying the scale factors to the reference PPA metric to determine the trial PPA metric for the trial design point. The method further comprises recommending a trial design point based on the estimated trial PPA metric and the received target PPA metric.Type: ApplicationFiled: April 3, 2015Publication date: October 6, 2016Inventors: Prasad Subramaniam, Hao Nham, Rakesh Chadha, Ferran Martorell
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Publication number: 20160292314Abstract: In one aspect, a method for providing design point recommendations for an integrated circuit (IC) design is disclosed. The method comprises receiving an IC design along with a reference PPA (power, performance, area) metric at a reference design point, and a target PPA metric. The method also comprises estimating trial PPA metrics for the IC design at multiple design points, wherein estimating trial PPA metric at each design point includes accessing a PPA database containing PPA metrics for multiple test components, determining scale factors from the reference design point to the trial design point for test components equivalent to components of the IC design, and applying the scale factors to the reference PPA metric to determine the trial PPA metric for the trial design point. The method further comprises recommending a trial design point based on the estimated trial PPA metric and the received target PPA metric.Type: ApplicationFiled: April 3, 2015Publication date: October 6, 2016Inventors: Prasad Subramaniam, Hao Nham, Rakesh Chadha, Ferran Martorell
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Patent number: 9460255Abstract: In one aspect, a method for providing design point recommendations for an integrated circuit (IC) design is disclosed. The method comprises receiving an IC design along with a reference PPA (power, performance, area) metric at a reference design point, and a target PPA metric. The method also comprises estimating trial PPA metrics for the IC design at multiple design points, wherein estimating trial PPA metric at each design point includes accessing a PPA database containing PPA metrics for multiple test components, determining scale factors from the reference design point to the trial design point for test components equivalent to components of the IC design, and applying the scale factors to the reference PPA metric to determine the trial PPA metric for the trial design point. The method further comprises recommending a trial design point based on the estimated trial PPA metric and the received target PPA metric.Type: GrantFiled: April 3, 2015Date of Patent: October 4, 2016Assignee: eSilicon CorporationInventors: Prasad Subramaniam, Hao Nham, Rakesh Chadha, Ferran Martorell
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Patent number: 9460257Abstract: In one aspect, a method for providing design point recommendations for an integrated circuit (IC) design is disclosed. The method comprises receiving an IC design along with a reference PPA (power, performance, area) metric at a reference design point, and a target PPA metric. The method also comprises estimating trial PPA metrics for the IC design at multiple design points, wherein estimating trial PPA metric at each design point includes accessing a PPA database containing PPA metrics for multiple test components, determining scale factors from the reference design point to the trial design point for test components equivalent to components of the IC design, and applying the scale factors to the reference PPA metric to determine the trial PPA metric for the trial design point. The method further comprises recommending a trial design point based on the estimated trial PPA metric and the received target PPA metric.Type: GrantFiled: April 3, 2015Date of Patent: October 4, 2016Assignee: eSilicon CorporationInventors: Prasad Subramaniam, Hao Nham, Rakesh Chadha, Ferran Martorell
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Patent number: 9460254Abstract: In one aspect, a method for providing design point recommendations for an integrated circuit (IC) design is disclosed. The method comprises receiving an IC design along with a reference PPA (power, performance, area) metric at a reference design point, and a target PPA metric. The method also comprises estimating trial PPA metrics for the IC design at multiple design points, wherein estimating trial PPA metric at each design point includes accessing a PPA database containing PPA metrics for multiple test components, determining scale factors from the reference design point to the trial design point for test components equivalent to components of the IC design, and applying the scale factors to the reference PPA metric to determine the trial PPA metric for the trial design point. The method further comprises recommending a trial design point based on the estimated trial PPA metric and the received target PPA metric.Type: GrantFiled: April 3, 2015Date of Patent: October 4, 2016Assignee: eSilicon CorporationInventors: Prasad Subramaniam, Hao Nham, Rakesh Chadha, Ferran Martorell
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Patent number: 9460256Abstract: In one aspect, a method for providing design point recommendations for an integrated circuit (IC) design is disclosed. The method comprises receiving an IC design along with a reference PPA (power, performance, area) metric at a reference design point, and a target PPA metric. The method also comprises estimating trial PPA metrics for the IC design at multiple design points, wherein estimating trial PPA metric at each design point includes accessing a PPA database containing PPA metrics for multiple test components, determining scale factors from the reference design point to the trial design point for test components equivalent to components of the IC design, and applying the scale factors to the reference PPA metric to determine the trial PPA metric for the trial design point. The method further comprises recommending a trial design point based on the estimated trial PPA metric and the received target PPA metric.Type: GrantFiled: April 3, 2015Date of Patent: October 4, 2016Assignee: eSilicon CorporationInventors: Prasad Subramaniam, Hao Nham, Rakesh Chadha, Ferran Martorell