Patents by Inventor Prasad Vajjhala

Prasad Vajjhala has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7512695
    Abstract: A method and system of communicating data between a source interconnect device and a destination interconnect device are defined. The method includes adding an identification component to the data at the source interconnect device prior to communicating the data, and extracting the identification component at the destination interconnect device. The identification component is then processed at the destination interconnect device, the identification component relating to the contents of the data. The invention extends to a machine-readable medium embodying a set of instructions for executing the method and to an interconnect device.
    Type: Grant
    Filed: May 7, 2003
    Date of Patent: March 31, 2009
    Assignee: Avago Technologies General IP (Singapore) Pte. Ltd.
    Inventors: Mohamed Magdy Talaat, Rick Reeve, Richard L. Schober, Prasad Vajjhala, Yolin Lih, Dev Datta
  • Patent number: 7124241
    Abstract: A write hub is described. The write hub has a plurality of registers. Each one of the registers helps generate a write address to a different memory bank from amongst a plurality of memory banks. Each of the registers are arranged in a ring so that each register can pass a pointer value toward a next register within the ring. The ring of registers further comprise a multiplexer between each of the registers. Each multiplexer has an output path that flows toward a next register within the ring relative to the multiplexer. Each multiplexer can introduce a pointer value to the ring at a next register within the ring.
    Type: Grant
    Filed: May 7, 2003
    Date of Patent: October 17, 2006
    Assignee: Avago Technologies General IP (Singapore) Pte.Ltd.
    Inventors: Rick Reeve, Richard L. Schober, Ian Colloff, Prasad Vajjhala
  • Patent number: 7111101
    Abstract: A method of port numbering in an interconnect device includes loading a port configuration value from a memory device. One or more ports and subports are enabled according to the configuration value. Contiguous logical port numbers are assigned to the one or more ports and subports included in the interconnect device. A mapping request is received; and a mapped response associated with the mapping request is provided to an entity.
    Type: Grant
    Filed: May 7, 2003
    Date of Patent: September 19, 2006
    Assignee: Ayago Technologies General IP (Singapore) Ptd. Ltd.
    Inventors: Daniel Bourke, Prasad Vajjhala, Norman C. Chou
  • Patent number: 7043569
    Abstract: In one embodiment, a system for configuring an interconnect device includes a non-volatile storage device to store configuration data associated with the interconnect device and a configuration interface to request the configuration data from the non-volatile storage device. Further, the system includes an initialization module to query the configuration interface for the configuration data and to distribute the configuration data provided by the configuration interface to multiple units within the interconnect device.
    Type: Grant
    Filed: September 7, 2001
    Date of Patent: May 9, 2006
    Inventors: Norman C. Chou, Prasad Vajjhala, Richard Schober, Laura Randall, Ian G. Collof
  • Patent number: 6957312
    Abstract: In one embodiment, a method for facilitating detection of, and recovery from, data contamination in a non-volatile storage device coupled to an interconnect device includes receiving data to be written to a content area on a non-volatile storage device coupled to an interconnect device, updating a contamination indicator stored in a supplemental area of the non-volatile storage device with a first value indicating potential data contamination in the content area, and transferring the data to the non-volatile storage device for a write to the content area. Further, if a determination is made that the write of the transferred data has completed, the contamination indicator is updated with a second value indicating lack of data contamination in the content area.
    Type: Grant
    Filed: May 7, 2003
    Date of Patent: October 18, 2005
    Assignee: Agilent Technologies, Inc.
    Inventors: Norman C. Chou, Prasad Vajjhala, Daniel Bourke
  • Publication number: 20050021797
    Abstract: A method and system of communicating data between a source interconnect device and a destination interconnect device are defined. The method includes adding an identification component to the data at the source interconnect device prior to communicating the data, and extracting the identification component at the destination interconnect device. The identification component is then processed at the destination interconnect device, the identification component relating to the contents of the data. The invention extends to a machine-readable medium embodying a set of instructions for executing the method and to an interconnect device.
    Type: Application
    Filed: May 7, 2003
    Publication date: January 27, 2005
    Inventors: Mohamed Talaat, Rick Reeve, Richard Schober, Prasad Vajjhala, Yolin Lih, Dev Datta
  • Publication number: 20040225734
    Abstract: A method and system of communicating data between a plurality of interconnect devices are described. The method includes allocating a sequence number associated with each grant authorizing a source interconnect device to communicate the data to a destination interconnect device. The sequence number of a queued grant is then with a reference sequence number and, in response to the comparison, the data is communicated. In one embodiment, the sequence number is a grant sequence number that defines a sequence in which each grant is to be executed in response to a comparison with a reference transmit sequence number.
    Type: Application
    Filed: May 7, 2003
    Publication date: November 11, 2004
    Inventors: Richard L. Schober, Rick Reeve, Prasad Vajjhala
  • Patent number: 6785854
    Abstract: A system and method facilitates simplified debugging of internal component scan testing. In an example embodiment, a TAP controlled internal scan test intermediate debugging system includes an intermediate TAP controller internal scan test system, design circuit blocks, a scan test chain primary input pin, a scan test chain final output pin. The components of the intermediate TAP controlled internal scan test debugging system cooperatively operate to facilitate debugging of faults through extraction of intermediate scan test chain signals. The intermediate TAP controller internal scan test system transmits an indicated intermediate scan test chain signal off of the IC as a TAP test data out (TDO) signal. The intermediate TAP controller internal scan test system utilizes an internal scan observe register to store information indicating which intermediate internal scan test chain signal to forward as a TAP TDO signal.
    Type: Grant
    Filed: October 2, 2000
    Date of Patent: August 31, 2004
    Assignee: Koninklijke Philips Electronics N.V.
    Inventors: Ken Jaramillo, Prasad Vajjhala
  • Publication number: 20040030763
    Abstract: Internal memory elements of vendor-specific network devices are made available using standardized network protocol packets. In accordance with the invention, reserved values of an attribute identifier field may be mapped to implementation-specific nodes within a particular manufacturer's network device, while a set of reserved attribute modifier values may be mapped to implementation-specific memory elements within the node specified by the value of the attribute identifier. Access to implementation-specific device internals is therefore made possible using the standard network protocol.
    Type: Application
    Filed: August 8, 2002
    Publication date: February 12, 2004
    Inventors: Venitha L. Manter, Norman Chou, Prasad Vajjhala, S. Paul Tucker