Abstract: An electronic device can include a bidirectional HEMT. In an aspect, the electronic device can include a pair of switch gate and blocking gate electrodes, wherein the switch gate electrodes are not electrically connected to the blocking gate electrodes, and the first blocking, first switch, second blocking, and second switch gate electrodes are on the same die. In another aspect, the electronic device can include shielding structures having different numbers of laterally extending portions. In a further aspect, the electronic device can include a gate electrode and a shielding structure, wherein a portion of the shielding structure defines an opening overlying the gate electrode.

Abstract: In one embodiment, a semiconductor device is formed to include a gate structure extending into a semiconductor material that is underlying a first region of semiconductor material. The gate structure includes a conductor and also a gate insulator that has a first portion positioned between the gate conductor and a first portion of the semiconductor material that underlies the gate conductor. The first portion of the semiconductor material is configured to form a channel region of the transistor which underlies the gate conductor. The gate structure may also include a shield conductor overlying the gate conductor and having a shield insulator between the shield conductor and the gate conductor. The shield insulator may also have a second portion positioned between the shield conductor and a second portion of the gate insulator and a third portion overlying the shield conductor.

Abstract: In one embodiment, a vertical insulated-gate field effect transistor includes a feature embedded within a control electrode. The feature is placed within the control electrode to induce stress within predetermined regions of the transistor.

Abstract: In one embodiment, a structure for a trench power field effect transistor device with controlled, shallow, abrupt, body contact regions.

Abstract: In one embodiment, a group III-V transistor structure includes a heterostructure disposed on a semiconductor substrate. A first current carrying electrode and a second current carrying electrode are disposed adjacent a major surface of the heterostructure and a control electrode is disposed between the first and second current carrying electrode. A clamping device is integrated with the group III-V transistor structure and is electrically connected to the first current carrying electrode a third electrode to provide a secondary current path during, for example, an electrical stress event.

Abstract: In one embodiment, a cascode rectifier structure includes a group III-V semiconductor structure includes a heterostructure disposed on a semiconductor substrate. A first current carrying electrode and a second current carrying electrode are disposed adjacent a major surface of the heterostructure and a control electrode is disposed between the first and second current carrying electrode. A rectifier device is integrated with the group III-V semiconductor structure and is electrically connected to the first current carrying electrode and to a third electrode. The control electrode is further electrically connected to the semiconductor substrate and the second current path is generally perpendicular to a primary current path between the first and second current carrying electrodes.

Abstract: A shielding structure for a semiconductor device includes a plurality of trenches. The trenches include passivation liners and shield electrodes, which are formed therein. In one embodiment, the shielding structure is placed beneath a control pad. In another embodiment, the shielding structure is placed beneath a control runner.

Abstract: In one embodiment, a vertical insulated-gate field effect transistor includes a shield electrode formed in trench structure within a semiconductor material. A gate electrode is isolated from the semiconductor material using gate insulating layers. Before the shield electrode is formed, spacer layers can be used form shield insulating layers along portions of the trench structure. The shield insulating layers are thicker than the gate insulating layers. In another embodiment, the shield insulating layers have variable thickness.

Abstract: In one embodiment, Group III-nitride materials are used to form a semiconductor device. A fin structure is formed in the Group III-nitride material, and a gate structure, source electrodes and drain electrodes are formed in spaced relationship to the fin structure. The fin structure provides both polar and semi-polar 2DEG regions. In one embodiment, the gate structure is configured to control current flow in the polar 2DEG region. Shield conductor layers are included above the gate structure and in spaced relationship with drain regions of the semiconductor device.

Abstract: An electronic device can include a substrate including an underlying doped region and a semiconductor layer overlying the substrate. A trench can have a sidewall and extend at least partly through the semiconductor layer. The electronic device can further include a first conductive structure adjacent to the underlying doped region, an insulating layer, and a second conductive structure within the trench. The insulating layer can be disposed between the first and second conductive structures, and the first conductive structure can be disposed between the insulating layer and the underlying doped region. Processes of forming the electronic device may be performed such that the first conductive structure includes a conductive fill material or a doped region within the semiconductor layer. The first conductive structure can allow the underlying doped region to be farther from the channel region and allow RDSON to be lower for a given BVDSS.

Abstract: In one embodiment, Group III-nitride materials are used to form a semiconductor device. A fin structure is formed in the Group III-nitride material, and a gate structure, source electrodes and drain electrodes are formed in spaced relationship to the fin structure. The fin structure provides both polar and semi-polar 2DEG regions. In one embodiment, the gate structure is configured to control current flow in the polar 2DEG region. Shield conductor layers are included above the gate structure and in spaced relationship with drain regions of the semiconductor device.

Abstract: In one embodiment, a structure for a semiconductor device has trench shield electrodes formed above and below a gate electrode. The structure can be configured to function as a bidirectional power field effect transistor.

Abstract: In one embodiment, a method for forming a semiconductor device includes forming trench and a dielectric layer along surfaces of the trench. A shield electrode is formed in a lower portion of the trench and the dielectric layer is removed from upper sidewall surfaces of the trench. A gate dielectric layer is formed along the upper surfaces of the trench. Oxidation-resistant spacers are formed along the gate dielectric layer. Thereafter, an interpoly dielectric layer is formed above the shield electrode using localized oxidation. The oxidation step increases the thickness of lower portions of the gate dielectric layer. The oxidation-resistant spacers are removed before forming a gate electrode adjacent the gate dielectric layer.

Abstract: An electronic device can include a semiconductor layer overlying a substrate and having a primary surface and a thickness, wherein a trench extends through at least approximately 50% of the thickness of semiconductor layer to a depth. The electronic device can further include a conductive structure within the trench, wherein the conductive structure extends at least approximately 50% of the depth of the trench. The electronic device can still further include a vertically-oriented doped region within the semiconductor layer adjacent to and electrically insulated from the conductive structure; and an insulating layer disposed between the vertically-oriented doped region and the conductive structure. A process of forming an electronic device can include patterning a semiconductor layer to define a trench extending through at least approximately 50% of the thickness of the semiconductor layer and forming a vertically-oriented doped region after patterning the semiconductor layer to define the trench.

Abstract: An electronic device can include a transistor structure, including a patterned semiconductor layer overlying a substrate and having a primary surface, wherein the patterned semiconductor layer defines a first trench and a second trench that extend from the primary surface towards the substrate. The electronic device can further include a first conductive electrode and a gate electrode within the first trench. The electronic device can still further include a second conductive electrode within the second trench. The electronic device can include a source region within the patterned semiconductor layer and disposed between the first and second trenches. The electronic device can further include a body contact region within the patterned semiconductor layer and between the first and second trenches, wherein the body contact region is spaced apart from the primary surface. Processes of forming the electronic device can take advantage of forming all trenches during processing sequence.

Abstract: In one embodiment, a vertical insulated-gate field effect transistor includes a feature embedded within a control electrode. The feature is placed within the control electrode to induce stress within predetermined regions of the transistor.

Abstract: In one embodiment, a vertical insulated-gate field effect transistor includes a shield electrode formed in trench structure within a semiconductor material. A gate electrode is isolated from the semiconductor material using gate insulating layers. Before the shield electrode is formed, spacer layers can be used form shield insulating layers along portions of the trench structure. The shield insulating layers are thicker than the gate insulating layers. In another embodiment, the shield insulating layers have variable thickness.

Abstract: An electronic device can include a semiconductor layer having a primary surface, and a Schottky contact comprising a metal-containing member in contact with a horizontally-oriented lightly doped region within the semiconductor layer and lying adjacent to the primary surface. In an embodiment, the metal-containing member lies within a recess in the semiconductor layer and contacts the horizontally-oriented lightly doped region along a sidewall of the recess. In other embodiment, the Schottky contact may not be formed within a recess, and a doped region may be formed within the semiconductor layer under the horizontally-oriented lightly doped region and have a conductivity type opposite the horizontally-oriented lightly doped region. The Schottky contacts can be used in conjunction with power transistors in a switching circuit, such as a high-frequency voltage regulator.

Abstract: In one embodiment, a vertical insulated-gate field effect transistor includes a shield electrode formed in trench structure within a semiconductor material. A gate electrode is isolated from the semiconductor material using gate insulating layers. Before the shield electrode is formed, spacer layers can be used form shield insulating layers along portions of the trench structure. The shield insulating layers are thicker than the gate insulating layers. In another embodiment, the shield insulating layers have variable thickness.

Abstract: In one embodiment, a vertical insulated-gate field effect transistor includes a feature embedded within a control electrode. The feature is placed within the control electrode to induce stress within predetermined regions of the transistor.