Abstract: Transaction layer link down handling for Peripheral Component Interconnect (PCI) Express. A link between an input/output (I/O) controller port of an I/O controller and a device port of a device is initialized, wherein the link includes a physical layer, a data link layer, and a transaction layer. The transaction layer is restored after a data link down condition without software intervention.

Abstract: In some embodiments, a circuit includes an oscillator circuit and a control circuit. The oscillator circuit generates a clock signal and includes a plurality of selectable delay circuits. The control circuit receives the clock signal from the oscillator and a reference signal. The control circuit provides a control signal to the oscillator circuit to activate one or more of the plurality of selectable delay circuits to change the frequency of the clock signal. In some embodiments, a method includes generating a clock signal in an oscillator circuit, processing the clock signal to generate a control signal, and activating one or more of a plurality of selectable delay circuits in the oscillator circuit, in response to the control signal.

Abstract: In some embodiments, a circuit includes an oscillator circuit, a control circuit, and a synchronization circuit. The oscillator circuit generates a clock signal and includes a selectable delay circuit. The control circuit receives the clock signal from the oscillator and a reference signal. The control circuit provides a control signal to the synchronization circuit which provides a control signal that has been synchronized to the oscillator circuit to activate the selectable delay circuit to change the frequency of the clock signal. In some embodiments, a method includes generating a clock signal in an oscillator circuit, and synchronizing activation of a selectable delay circuit in the oscillator circuit to a local clock signal.

Abstract: In some embodiments, a circuit includes an oscillator circuit and a control circuit. The oscillator circuit generates a clock signal and includes a selectable delay circuit. The control circuit receives the clock signal from the oscillator and a reference signal. The control circuit provides a control signal to the oscillator circuit to activate the selectable delay circuit to change the frequency of the clock signal. In some embodiments, a method includes generating a clock signal in an oscillator circuit, processing the clock signal to generate a control signal, and activating a selectable delay circuit in the oscillator circuit, in response to the control signal.

Abstract: In some embodiments, a circuit includes an oscillator circuit and a control circuit. The oscillator circuit generates a clock signal and includes a selectable delay circuit. The control circuit receives the clock signal from the oscillator and a reference signal. The control circuit provides a control signal to the oscillator circuit to activate the selectable delay circuit to change the frequency of the clock signal. In some embodiments, a method includes generating a clock signal in an oscillator circuit, processing the clock signal to generate a control signal, and activating a selectable delay circuit in the oscillator circuit, in response to the control signal.

Abstract: In some embodiments, a circuit includes an oscillator circuit, a control circuit, and a synchronization circuit. The oscillator circuit generates a clock signal and includes a selectable delay circuit. The control circuit receives the clock signal from the oscillator and a reference signal. The control circuit provides a control signal to the synchronization circuit which provides a control signal that has been synchronized to the oscillator circuit to activate the selectable delay circuit to change the frequency of the clock signal. In some embodiments, a method includes generating a clock signal in an oscillator circuit, and synchronizing activation of a selectable delay circuit in the oscillator circuit to a local clock signal.

Abstract: In some embodiments, a circuit includes an oscillator circuit and a control circuit. The oscillator circuit generates a clock signal and includes a plurality of selectable delay circuits. The control circuit receives the clock signal from the oscillator and a reference signal. The control circuit provides a control signal to the oscillator circuit to activate one or more of the plurality of selectable delay circuits to change the frequency of the clock signal. In some embodiments, a method includes generating a clock signal in an oscillator circuit, processing the clock signal to generate a control signal, and activating one or more of a plurality of selectable delay circuits in the oscillator circuit, in response to the control signal.

Abstract: According to one embodiment, an integrated circuit is disclosed that includes a plurality of functional unit blocks (FUBs), wherein each of the plurality of FUBs further includes a clock gated circuit and a clock gating circuit. The clock gating circuit immediately ungates clock signals to be received at the clock gated circuit whenever the clock gated circuit is to transition from an idle state to a non-idle state. According to a further embodiment, the clock gating circuit also immediately gates the clock signals whenever the clock gated circuit is to transition from a non-idle state to the idle state.