Patents by Inventor Prasanna Dighe
Prasanna Dighe has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 11682570Abstract: A controller is configured to perform at least a first characterization process prior to at least one discrete backside film deposition process on a semiconductor wafer; perform at least an additional characterization process following the at least one discrete backside film deposition process; determine at least one of a film force or one or more in-plane displacements for at least one discrete backside film deposited on the semiconductor wafer via the at least one discrete backside film deposition process based on the at least the first characterization process and the at least the additional characterization process; and provide at least one of the film force or the one or more in-plane displacements to at least one process tool via at least one of a feed forward loop or a feedback loop to improve performance of one or more fabrication processes.Type: GrantFiled: September 20, 2021Date of Patent: June 20, 2023Assignee: KLA CorporationInventors: Pradeep Vukkadala, Mark D. Smith, Ady Levy, Prasanna Dighe, Dieter Mueller
-
Patent number: 11441893Abstract: A system for analyzing a sample includes an illumination source with a plurality of transmitting optical fibers optically coupled to the illumination source and a detector with a plurality of receiving optical fibers optically coupled to the detector. The system further includes a plurality of probes coupled to respective ones of the plurality of transmitting optical fibers and respective ones of the plurality of receiving optical fibers. The plurality of probes are configured to illuminate respective portions of a surface of the sample and configured to receive illumination reflected, refracted, or radiated from the respective portions of the surface of the sample. The system may further include one or more switches and/or splitters configured to optically couple respective ones of the plurality of transmitting optical fibers to the illumination source and/or configured to optically couple respective ones of the plurality of receiving optical fibers to the detector.Type: GrantFiled: June 26, 2018Date of Patent: September 13, 2022Assignee: KLA CorporationInventors: Prasanna Dighe, Dieter Mueller, Dong Chen, Dengpeng Chen, Steve Zamek, Daniel Kavaldjiev, Alexander Buettner
-
Publication number: 20220005714Abstract: A controller is configured to perform at least a first characterization process prior to at least one discrete backside film deposition process on a semiconductor wafer; perform at least an additional characterization process following the at least one discrete backside film deposition process; determine at least one of a film force or one or more in-plane displacements for at least one discrete backside film deposited on the semiconductor wafer via the at least one discrete backside film deposition process based on the at least the first characterization process and the at least the additional characterization process; and provide at least one of the film force or the one or more in-plane displacements to at least one process tool via at least one of a feed forward loop or a feedback loop to improve performance of one or more fabrication processes.Type: ApplicationFiled: September 20, 2021Publication date: January 6, 2022Inventors: Pradeep Vukkadala, Mark D. Smith, Ady Levy, Prasanna Dighe, Dieter Mueller
-
Patent number: 11164768Abstract: A controller is configured to perform at least a first characterization process prior to at least one discrete backside film deposition process on a semiconductor wafer; perform at least an additional characterization process following the at least one discrete backside film deposition process; determine at least one of a film force or one or more in-plane displacements for at least one discrete backside film deposited on the semiconductor wafer via the at least one discrete backside film deposition process based on the at least the first characterization process and the at least the additional characterization process; and provide at least one of the film force or the one or more in-plane displacements to at least one process tool via at least one of a feed forward loop or a feedback loop to improve performance of one or more fabrication processes.Type: GrantFiled: June 26, 2018Date of Patent: November 2, 2021Assignee: KLA CorporationInventors: Pradeep Vukkadala, Mark D. Smith, Ady Levy, Prasanna Dighe, Dieter Mueller
-
Patent number: 11049720Abstract: A method of using removable opaque coating for accurate optical topography measurements on top surfaces of transparent films includes: depositing a highly reflective coating onto a top surface of a wafer, measuring topography on the highly reflective coating, and removing the highly reflective coating from the wafer. The highly reflective coating includes an organic material. The highly reflective coating comprises a refractive index value between one and two. The highly reflective coating comprises a complex wavelength greater than one at six-hundred and thirty-five nanometers. The highly reflective coating reflects at least twenty percent of incident light. The highly reflective coating when deposited maintains an underlayer pattern topography at a resolution of forty by forty micrometers. The highly reflective coating does not cause destructive stress to the wafer.Type: GrantFiled: October 9, 2019Date of Patent: June 29, 2021Assignee: KLA CorporationInventors: Dieter Mueller, Prasanna Dighe, Xiaomeng Shen, Jason Saito
-
Publication number: 20200126786Abstract: A method of using removable opaque coating for accurate optical topography measurements on top surfaces of transparent films includes: depositing a highly reflective coating onto a top surface of a wafer, measuring topography on the highly reflective coating, and removing the highly reflective coating from the wafer. The highly reflective coating includes an organic material. The highly reflective coating comprises a refractive index value between one and two. The highly reflective coating comprises a complex wavelength greater than one at six-hundred and thirty-five nanometers. The highly reflective coating reflects at least twenty percent of incident light. The highly reflective coating when deposited maintains an underlayer pattern topography at a resolution of forty by forty micrometers. The highly reflective coating does not cause destructive stress to the wafer.Type: ApplicationFiled: October 9, 2019Publication date: April 23, 2020Inventors: Dieter Mueller, Prasanna Dighe, Xiaomeng Shen, Jason Saito
-
Patent number: 10545412Abstract: A method to collect data and train, validate and deploy statistical models to predict overlay errors using patterned wafer geometry data and other relevant information includes selecting a training wafer set, measuring at multiple lithography steps and calculating geometry differences, applying a plurality of predictive models to the training wafer geometry differences and comparing predicted overlay to the measured overlay on the training wafer set. The most accurate predictive model is identified and the results fed-forward to the lithography scanner tool which can correct for these effects and reduce overlay errors during the wafer scan-and-expose processes.Type: GrantFiled: March 5, 2015Date of Patent: January 28, 2020Assignee: KLA-Tencor CorporationInventors: Wei Chang, Krishna Rao, Joseph Gutierrez, Ramon Olavarria, Craig MacNaughton, Amir Azordegan, Prasanna Dighe
-
Publication number: 20190331592Abstract: A system for analyzing a sample includes an illumination source with a plurality of transmitting optical fibers optically coupled to the illumination source and a detector with a plurality of receiving optical fibers optically coupled to the detector. The system further includes a plurality of probes coupled to respective ones of the plurality of transmitting optical fibers and respective ones of the plurality of receiving optical fibers. The plurality of probes are configured to illuminate respective portions of a surface of the sample and configured to receive illumination reflected, refracted, or radiated from the respective portions of the surface of the sample. The system may further include one or more switches and/or splitters configured to optically couple respective ones of the plurality of transmitting optical fibers to the illumination source and/or configured to optically couple respective ones of the plurality of receiving optical fibers to the detector.Type: ApplicationFiled: June 26, 2018Publication date: October 31, 2019Inventors: Prasanna Dighe, Dieter Mueller, Dong Chen, Dengpeng Chen, Steve Zamek, Daniel Kavaldjiev, Alexander Buettner
-
Publication number: 20190333794Abstract: A controller is configured to perform at least a first characterization process prior to at least one discrete backside film deposition process on a semiconductor wafer; perform at least an additional characterization process following the at least one discrete backside film deposition process; determine at least one of a film force or one or more in-plane displacements for at least one discrete backside film deposited on the semiconductor wafer via the at least one discrete backside film deposition process based on the at least the first characterization process and the at least the additional characterization process; and provide at least one of the film force or the one or more in-plane displacements to at least one process tool via at least one of a feed forward loop or a feedback loop to improve performance of one or more fabrication processes.Type: ApplicationFiled: June 26, 2018Publication date: October 31, 2019Inventors: Pradeep Vukkadala, Mark D. Smith, Ady Levy, Prasanna Dighe, Dieter Mueller
-
Publication number: 20170017162Abstract: A method to collect data and train, validate and deploy statistical models to predict overlay errors using patterned wafer geometry data and other relevant information includes selecting a training wafer set, measuring at multiple lithography steps and calculating geometry differences, applying a plurality of predictive models to the training wafer geometry differences and comparing predicted overlay to the measured overlay on the training wafer set. The most accurate predictive model is identified and the results fed-forward to the lithography scanner tool which can correct for these effects and reduce overlay errors during the wafer scan-and-expose processes.Type: ApplicationFiled: March 5, 2015Publication date: January 19, 2017Applicant: KLA-Tenor CorporationInventors: Wei Chang, Krishna Rao, Joseph Gutierrez, Ramon Olavarria, Craig MacNaughton, Amir Azordegan, Prasanna Dighe
-
Patent number: 9087176Abstract: A method to collect data and train, validate and deploy statistical models to predict overlay errors using patterned wafer geometry data and other relevant information includes selecting a training wafer set, measuring at multiple lithography steps and calculating geometry differences, applying a plurality of predictive models to the training wafer geometry differences and comparing predicted overlay to the measured overlay on the training wafer set. The most accurate predictive model is identified and the results fed-forward to the lithography scanner tool which can correct for these effects and reduce overlay errors during the wafer scan-and-expose processes.Type: GrantFiled: March 20, 2014Date of Patent: July 21, 2015Assignee: KLA-Tencor CorporationInventors: Wei Chang, Krishna Rao, Joseph Gutierrez, Ramon Olavarria, Craig Macnaughton, Amir Azordegan, Prasanna Dighe, Jaydeep Sinha
-
Patent number: 8269960Abstract: Computer-implemented methods for inspecting and/or classifying a wafer are provided. One computer-implemented includes detecting defects on a wafer using one or more defect detection parameters, which are determined based on a non-spatially localized characteristic of the wafer that is determined using output responsive to light scattered from the wafer generated by an inspection system. Another computer-implemented method includes classifying a wafer based on a combination of a non-spatially localized characteristic of the wafer determined using output responsive to light scattered from the wafer generated by an inspection system and a spatially localized characteristic of the wafer determined using the output.Type: GrantFiled: July 24, 2008Date of Patent: September 18, 2012Assignee: KLA-Tencor Corp.Inventors: Juergen Reich, Louis Vintro, Prasanna Dighe, Andrew Steinbach, Daniel Kavaldjiev, Stephen Biellak
-
Publication number: 20100060888Abstract: Computer-implemented methods for inspecting and/or classifying a wafer are provided. One computer-implemented includes detecting defects on a wafer using one or more defect detection parameters, which are determined based on a non-spatially localized characteristic of the wafer that is determined using output responsive to light scattered from the wafer generated by an inspection system. Another computer-implemented method includes classifying a wafer based on a combination of a non-spatially localized characteristic of the wafer determined using output responsive to light scattered from the wafer generated by an inspection system and a spatially localized characteristic of the wafer determined using the output.Type: ApplicationFiled: July 24, 2008Publication date: March 11, 2010Applicant: KLA-TENCOR CORPORATIONInventors: Juergen Reich, Louis Vintro, Prasanna Dighe, Andrew Steinbach, Daniel Kavaldjiev, Stephen Biellak