Abstract: A pill management device includes a portable reservoir having a pill-receiving inlet and an access door spaced from the pill-receiving inlet, a pill-crushing mechanism disposed within the reservoir and configured to transform a solid pill, introduced via the pill-receiving inlet, to pill powder, and a locking mechanism in communication with the access door and the pill-receiving inlet for preventing unauthorized access to the pill powder housed within the reservoir. Advantageously, the locking mechanism locks the access door and the pill-receiving inlet.

Abstract: Queue resource sharing for an input/output controller. A shared resource queue is associated with a plurality of ports. The shared resource queue includes a plurality of sections allocated for use by at least one of the plurality of ports based at least in part on a port bandwidth configuration of the plurality of ports.

Abstract: Transaction layer link down handling for Peripheral Component Interconnect (PCI) Express. A link between an input/output (I/O) controller port of an I/O controller and a device port of a device is initialized, wherein the link includes a physical layer, a data link layer, and a transaction layer. The transaction layer is restored after a data link down condition without software intervention.

Abstract: A method applicable to a host computer system having a system bus connected to a CPU, and a PCMCIA controller having status registers, means for supplying back off signals to the CPU and line buffers capable of being in a normal and high impedance state. A multi pin connector is located in each card socket and connected to a line buffer. Each connector has common address, data and control pins, power pins, ground pins longer than the data pins and card detect signal pins shorter than the signal pins. The first step is to detect the commencement of an insertion or removal of a PCMCIA card to or from a socket by monitoring the ground and card detect signal pins. After detection, commence termination of all CPU usage of common address, data and control lines by asserting a back off signal. Next, determine if the usage is terminated by monitoring the status registers in the controller. Next, place the common address, data and control lines in a high impedance state.