Patents by Inventor Prasanna Upadhyaya

Prasanna Upadhyaya has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10082819
    Abstract: A method includes providing a first voltage to a first output node during a first time interval, providing a second voltage to the first output node during a second time interval, and averaging the first and second voltages to provide a reference voltage to a second output node. The first voltage includes a proportional-to-absolute-temperature (PTAT) component, a complementary-to-absolute-temperature (CTAT) component, and a first residual offset component. The second voltage includes the PTAT component, the CTAT component, and a second residual offset component. An apparatus includes a discrete-time circuit to provide the first voltage to the first output node during the first time interval and to provide the second voltage to the first output node during the second time interval, and a filter to average the first and second voltages to provide the reference voltage to the second output node.
    Type: Grant
    Filed: October 26, 2016
    Date of Patent: September 25, 2018
    Assignee: Marvell World Trade Ltd.
    Inventors: Weiwei Xu, Prasanna Upadhyaya, Norman Liu, Xiaoyue Wang
  • Patent number: 9998137
    Abstract: An Analog-to-Digital Converter (ADC) device includes an input interface and conversion circuitry. The input interface is configured to receive an analog input signal. The conversion circuitry is configured to convert the analog input signal into a digital word by performing a sequence of iterations to determine respective bits of the digital word, wherein the sequence (i) progresses in descending order of bit significance of the bits, from a Most Significant Bit (MSB) to a Least Significant Bit (LSB), and (ii) repeats evaluation of a predefined number of Least-Significant Bits (LSBs) of the digital word multiple times, and determining a final value of the digital word by averaging the repeatedly-evaluated LSBs.
    Type: Grant
    Filed: September 17, 2017
    Date of Patent: June 12, 2018
    Assignee: MARVELL INTERNATIONAL LTD.
    Inventors: Xiang Li, Arvind Anumula Paramanandam, Prasanna Upadhyaya, Xiaoyue Wang
  • Publication number: 20170115684
    Abstract: A method includes providing a first voltage to a first output node during a first time interval, providing a second voltage to the first output node during a second time interval, and averaging the first and second voltages to provide a reference voltage to a second output node. The first voltage includes a proportional-to-absolute-temperature (PTAT) component, a complementary-to-absolute-temperature (CTAT) component, and a first residual offset component. The second voltage includes the PTAT component, the CTAT component, and a second residual offset component. An apparatus includes a discrete-time circuit to provide the first voltage to the first output node during the first time interval and to provide the second voltage to the first output node during the second time interval, and a filter to average the first and second voltages to provide the reference voltage to the second output node.
    Type: Application
    Filed: October 26, 2016
    Publication date: April 27, 2017
    Inventors: Weiwei XU, Prasanna UPADHYAYA, Norman LIU, Xiaoyue WANG
  • Patent number: 9369122
    Abstract: In aspects of a low phase noise technique for use with a crystal oscillator, a bias control circuit sets a bias voltage on the gate of a first transistor needed to sink or source an amount of current corresponding to a sensed common mode signal. The sensed common mode signal is sensed with a common mode sense circuit that is coupled across two ports of the crystal oscillator, and current is provided by a current source. The bias voltage is set by a bias controller that uses a second transistor coupled to the common mode sense circuit and the first transistor.
    Type: Grant
    Filed: August 27, 2015
    Date of Patent: June 14, 2016
    Assignee: Marvell World Trade Ltd.
    Inventors: Arvind Anumula Paramanandam, Norman Liu, Prasanna Upadhyaya, Xiaoyue Wang
  • Publication number: 20160072497
    Abstract: In aspects of a low phase noise technique for use with a crystal oscillator, a bias control circuit sets a bias voltage on the gate of a first transistor needed to sink or source an amount of current corresponding to a sensed common mode signal. The sensed common mode signal is sensed with a common mode sense circuit that is coupled across two ports of the crystal oscillator, and current is provided by a current source. The bias voltage is set by a bias controller that uses a second transistor coupled to the common mode sense circuit and the first transistor.
    Type: Application
    Filed: August 27, 2015
    Publication date: March 10, 2016
    Inventors: Arvind Anumula Paramanandam, Norman Liu, Prasanna Upadhyaya, Xiaoyue Wang