Abstract: A system receives a netlist representation of a circuit design. The system performs global routing using the netlist representation to generate a set of segments. A segment represents a portion of a net routed by the global routing. The system provides features extracted from a segment as input to one or more machine learning models. Each of the one or more machine learning models is configured to predict attributes of the input segment. The predicted attributes have more than a threshold correlation with corresponding attributes determined using detailed routing information. The system executes the one or more machine learning models to predict attributes each of a set of segments output by global routing of the netlist. The system determines parasitic resistance and parasitic capacitance values for nets of the circuit design based on the predicted attributes.

Abstract: A method and apparatus is described which allows efficient optimization of integrated circuit designs. By performing a global analysis of the circuit and identifying bottleneck nodes, optimization focuses on the nodes most likely to generate the highest return on investment and those that have the highest room for improvement. The identification of bottleneck nodes is seamlessly integrated into the timing analysis of the circuit design. Nodes are given a bottleneck number, which represents how important they are in meeting the objective function. By optimizing in order of highest bottleneck number, the optimization process converges quickly and will not get side-tracked by paths that cannot be improved.

Abstract: A method and apparatus are presented that can analyze the performance of an integrated circuit design at multiple corners, under multiple modes, and for multiple objectives efficiently and simultaneously. The extraction, timing analysis, and optimization functions are integrated into a mechanism that provides a novel problem formulation. A plurality of virtual timing graphs are maintained and updated simultaneously by providing a data structure that can efficiently store operating data for an arbitrary number of conditions at each node. This data structure is populated according to the design, and as optimizations are made, the operating data for all design conditions is updated simultaneously. Timing violations can be reported across all corners and modes. By integrating this multi-corner multi-mode analysis with circuit optimization, a convergent mechanism is provided. In this way, design constraints are evaluated simultaneously for an arbitrary number of design conditions.

Abstract: A system for calculating interconnect wire lateral capacitances in an automated integrated circuit design system subdivides the chip area of a circuit design to be placed and routed into a coarse grid of buckets. An estimate of congestion in each bucket is computed from an estimated amount of routing space available in the bucket and estimated consumption of routing resources by a global router. This congestion score is then used to determine the spacing of the wires in the bucket which is in turn used to estimate the capacitance of the wire segment in the bucket.