Abstract: The disclosed device for high-voltage-tolerant level shifters can include a level shifter device configured to shift an input signal from an input voltage range to an output voltage range, where a span from a bottom of the input voltage range to a top of the output voltage range is greater than a voltage differential tolerance of any of the plurality of transistors. Various other devices and systems are also disclosed.

Abstract: Transmitter circuitry receives a data signal and outputs a serial data signal. The transmitter circuitry includes serializer circuitry. The serializer circuitry includes data input circuitry and data serializer circuitry. The data input circuitry receives and outputs a first data signal based on a write pointer signal having a first value of values and a first clock signal. The data serializer circuitry configured to serialize the first data signal to generate a serial signal based on a read pointer signal having a second value of the values and a second clock signal. The first value differs from the second value.

Abstract: A method for driver calibration in die-to-die interfaces can include calibrating a delay lock loop of a delay line unit cell, by at least one processor, based on drive and load conditions of one or more driver unit cells of a physical layer of a die-to-die interconnect. The method can additionally include generating a clock signal, by the at least one processor, based on the delay lock loop. The method can further include communicating data, by the at least one processor, over the die-to-die interconnect based on the clock signal. Various other methods and systems are also disclosed.

Abstract: A circuit includes a first and second PMOS transistor serially coupled between a high voltage power supply and a pad, a gate of the first PMOS transistor coupled to a first signal from an internal circuit, the first signal configured to switch between a first voltage and the high voltage power supply, a gate and drain of the second PMOS transistor connected to an adaptive control node and the pad, respectively, and a first and second NMOS transistor serially coupled between the pad and a ground, a gate of the first NMOS transistor coupled to a second signal from the internal circuit, the second signal configured to switch between a second voltage and the ground, a gate and drain of the second NMOS transistor connected to the adaptive control node and the pad, respectively, wherein the adaptive control node is configured to switch between the first and second voltage.

Abstract: A signal processing circuit includes an analog front-end circuit and a digital delay circuit. The analog circuit receives a clock signal and provides a compensated clock signal. The digital delay circuit is coupled to the analog front-end circuit and provides a compensated sample clock signal in response to delaying the compensated clock signal. The analog circuit measures a variation of a power supply voltage and adjusts a gain through the analog circuit according to a measured variation of the power supply voltage.

Abstract: Transmitter circuitry receives a data signal and outputs a serial data signal. The transmitter circuitry includes serializer circuitry. The serializer circuitry includes data input circuitry and data serializer circuitry. The data input circuitry receives and outputs a first data signal based on a write pointer signal having a first value of values and a first clock signal. The data serializer circuitry configured to serialize the first data signal to generate a serial signal based on a read pointer signal having a second value of the values and a second clock signal. The first value differs from the second value.

Abstract: The disclosed device for high-voltage-tolerant level shifters can include a level shifter device configured to shift an input signal from an input voltage range to an output voltage range, where a span from a bottom of the input voltage range to a top of the output voltage range is greater than a voltage differential tolerance of any of the plurality of transistors. Various other devices and systems are also disclosed.

Abstract: An accelerated processor includes a processor core die including a plurality of compute units, the plurality of compute units including a first level (L1) cache. The accelerated processor also includes a plurality of memory cache dies coupled to the processor core die, the plurality of memory cache dies including a last level cache (LLC) such as a level 3 (L3) cache. The accelerated processor includes an LLC controller to issue a cache access request to the LLC and, based on a latency of the cache access request, direct the cache access request to a subset of the plurality of memory cache dies.

Abstract: The disclosed device includes a data path having multiple transmission drivers. The device also includes a controller that is configured to tune each of the transmission drivers to a signal speed of a reference transmission driver. Various other methods, systems, and computer-readable media are also disclosed.

Abstract: An accelerated processor includes a processor core die including a plurality of compute units, the plurality of compute units including a first level (L1) cache. The accelerated processor also includes a plurality of memory cache dies coupled to the processor core die, the plurality of memory cache dies including a last level cache (LLC) such as a level 3 (L3) cache. The accelerated processor includes an LLC controller to issue a cache access request to the LLC and, based on a latency of the cache access request, direct the cache access request to a subset of the plurality of memory cache dies.

Abstract: A method for driver calibration in die-to-die interfaces can include calibrating a delay lock loop of a delay line unit cell, by at least one processor, based on drive and load conditions of one or more driver unit cells of a physical layer of a die-to-die interconnect. The method can additionally include generating a clock signal, by the at least one processor, based on the delay lock loop. The method can further include communicating data, by the at least one processor, over the die-to-die interconnect based on the clock signal. Various other methods and systems are also disclosed.

Abstract: A disclosed method for improving latency or power consumption may include (i) receiving, at a power-state processing circuit, a power-state signal indicating whether a processing unit is entering a low-power-state, (ii) transmitting, in response to the power-state signal indicating that the processing unit is entering the low-power-state, a control signal from the power-state processing circuit to a latching circuit, and (iii) storing, by the latching circuit and in response to the control signal, a state of an input/output pad that is coupled to the processing unit. Various other apparatuses, systems, and methods are also disclosed.

Abstract: A signal processing circuit includes an analog front-end circuit and a digital delay circuit. The analog circuit receives a clock signal and provides a compensated clock signal. The digital delay circuit is coupled to the analog front-end circuit and provides a compensated sample clock signal in response to delaying the compensated clock signal. The analog circuit measures a variation of a power supply voltage and adjusts a gain through the analog circuit according to a measured variation of the power supply voltage.

Abstract: A clock circuit for clock gating using a cascaded clock gating control signal, including: a first B-latch accepting, as input, a clock gating control signal and enabled by a first clock signal; a second B-latch accepting, as input, an output from the first B-latch and enabled by a second clock signal; and a first logic outputting, based on the first B-latch, a first gated clock signal; and a second logic outputting, based on the second B-latch, a second gated clock signal.

Abstract: A semiconductor package includes a first die having a phase locked loop outputting a local clock signal and a strobe signal to a first transmit block of the first die. The strobe signal has a phase offset relative to the local clock signal. A second die is aligned with the first die so each of a first plurality of connection points of the first die is substantially equidistant to a corresponding connection point of a second plurality of connection points of the second die. A plurality of connection paths of a substantially same length couple a connection points of the first plurality of connection points to corresponding connection points of the second plurality of connection points. Different connection paths transmit data signals from the first die to the second die based on the local clock signal and transmit the strobe signal from the first die to the second die.

Abstract: A semiconductor package includes a first die having a phase locked loop outputting a local clock signal and a strobe signal to a first transmit block of the first die. The strobe signal has a phase offset relative to the local clock signal. A second die is aligned with the first die so each of a first plurality of connection points of the first die is substantially equidistant to a corresponding connection point of a second plurality of connection points of the second die. A plurality of connection paths of a substantially same length couple a connection points of the first plurality of connection points to corresponding connection points of the second plurality of connection points. Different connection paths transmit data signals from the first die to the second die based on the local clock signal and transmit the strobe signal from the first die to the second die.

Abstract: A semiconductor package for skew matching in a die-to-die interface, including: a first die; a second die aligned with the first die such that each connection point of a first plurality of connection points of the first die is substantially equidistant to a corresponding connection point of a second plurality of connection points of the second die; and a plurality of connection paths of a substantially same length, wherein each connection path of the plurality of connection paths couples a respective connection point of the first plurality of connection points to the corresponding connection point of the second plurality of connection points.

Abstract: Systems and techniques for applying voltage biases to gates of driver circuitry of an integrated circuit (IC) based on a detected bus voltage, IC supply voltage, or both are used to mitigate Electrical Over-Stress (EOS) issues in components of the driver circuitry caused, for instance, by high bus voltages in serial communication systems relative to maximum operating voltages of those components. A driver bias generator selectively applies bias voltages at gates of transistors of a stacked driver structure of an IC to prevent the voltage drop across any given transistor of the stacked driver structure from exceeding a predetermined threshold associated with the maximum operating voltage range of the transistors.

Abstract: A semiconductor package for skew matching in a die-to-die interface, including: a first die; a second die aligned with the first die such that each connection point of a first plurality of connection points of the first die is substantially equidistant to a corresponding connection point of a second plurality of connection points of the second die; and a plurality of connection paths of a substantially same length, wherein each connection path of the plurality of connection paths couples a respective connection point of the first plurality of connection points to the corresponding connection point of the second plurality of connection points.

Abstract: A clock circuit for clock gating using a cascaded clock gating control signal, including: a first B-latch accepting, as input, a clock gating control signal and enabled by a first clock signal; a second B-latch accepting, as input, an output from the first B-latch and enabled by a second clock signal; and a first logic outputting, based on the first B-latch, a first gated clock signal; and a second logic outputting, based on the second B-latch, a second gated clock signal.