Patents by Inventor Prasanth B

Prasanth B has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240141492
    Abstract: Susceptor assemblies having a susceptor base with a plurality of pockets formed in a surface thereof are described. Each of the pockets has a pocket edge angle in the range of 30 to 75° and a pocket edge radius in the range of 0.40±0.05 mm to 1.20 mm±0.05 mm. The pockets have a raised central region and an outer region that is deeper than the raised central region, relative to the surface of the surface of the susceptor base.
    Type: Application
    Filed: March 23, 2023
    Publication date: May 2, 2024
    Applicant: Applied Materials, Inc.
    Inventors: Prasanth Narayanan, Vijayabhaskara Venkatagiriyappa, Keiichi Tanaka, Ning Li, Robert B. Moore, Robert C. Linke, Mandyam Sriram, Mario D. Silvetti, Michael Racine, Tae Kwang Lee
  • Publication number: 20230259539
    Abstract: A system and method for automatically extracting and visualizing topics and information from a database of unstructured text documents. The method including: mapping each text document in the database into a latent vector in a latent space using a trained machine learning model; receiving a query from a user; mapping the query to the latent space; determining a predetermined set of text documents in the document database nearest to the query using a similarity metric on the latent vectors of each document; using a trained clustering machine learning model, determining cluster labels for the query and the set of the documents nearest to the query, the clustering labels representative of topics; and displaying a visualization of the query, the documents nearest to the query, and the cluster labels.
    Type: Application
    Filed: February 11, 2022
    Publication date: August 17, 2023
    Inventors: Kevin COURSE, Trefor W. EVANS, Prasanth B. NAIR
  • Patent number: 11360840
    Abstract: Embodiments of present disclosure relates to method and apparatus for performing redundancy analysis of a semiconductor device. For the redundancy analysis, plurality of banks in the semiconductor device is classified to be associated with a cluster from plurality of clusters. The classification is based on one or more attributes associated with the plurality of banks. Further, at least one cluster parameter for the plurality of clusters and at least one bank parameter for the plurality of banks, is determined. One or more algorithms is mapped with the plurality of clusters, based on the at least one cluster parameter and the at least one bank parameter. The redundancy analysis of at least one bank in the plurality of clusters is performed based on the mapping.
    Type: Grant
    Filed: July 20, 2020
    Date of Patent: June 14, 2022
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Atishay, Prasanth B
  • Patent number: 11113632
    Abstract: A system and method for performing operations on multi-dimensional functions using a machine learning model, the method including: receiving a problem formulation in input space; mapping the problem formulation from input space to one or more latent vectors or a set in latent feature space using a projection learned using the machine learning model; splitting the one or more latent vectors or set in latent space into a plurality of lower-dimensional groupings of latent features; performing one or more operations in latent space on each lower-dimensional groupings of latent features; combining each of the low-dimensional groupings; and outputting the combination for generating the prediction.
    Type: Grant
    Filed: January 21, 2021
    Date of Patent: September 7, 2021
    Assignee: THE GOVERNING COUNCIL OF THE UNIVERSITY OF TORONTO
    Inventors: Trefor W. Evans, Prasanth B. Nair
  • Publication number: 20210224146
    Abstract: Embodiments of present disclosure relates to method and apparatus for performing redundancy analysis of a semiconductor device. For the redundancy analysis, plurality of banks in the semiconductor device is classified to be associated with a cluster from plurality of clusters. The classification is based on one or more attributes associated with the plurality of banks. Further, at least one cluster parameter for the plurality of clusters and at least one bank parameter for the plurality of banks, is determined. One or more algorithms is mapped with the plurality of clusters, based on the at least one cluster parameter and the at least one bank parameter. The redundancy analysis of at least one bank in the plurality of clusters is performed based on the mapping.
    Type: Application
    Filed: July 20, 2020
    Publication date: July 22, 2021
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Atishay, Prasanth B