Abstract: A computer-implemented method for allocating registers for multi-core programs. The method includes generating core-specific programs for execution units of cores, wherein each program contains core-specific configurations. The method includes analyzing the core-specific programs to identify core-specific differences. The method includes creating a uniformized program that consolidates semantics of all programs for the execution units while retaining operations to account for core-specific differences. The method includes performing live range analysis of the uniformized program to identify active intervals for variables and creating segmented live ranges to partition the intervals into global and core-specific segments. The method includes allocating registers to the execution units using the segmented live ranges and multi-casting the uniformized program to the execution units of the cores.

Abstract: Described are techniques for reducing overhead controls. A loop tree is constructed from a program, such as a structured control flow program. Structured control flow refers to a programming concept where the flow of control to a block or region is based on single entry and single-exist methodology (SESE). A loop tree refers to a tree-like data structure that graphically represents loop(s) and/or an if-condition(s) in a program, such as a structured control flow program. A loop splitting operation or a loop unrolling operation may then be performed in connection with the node of the loop tree that is identified as having the highest benefit (ratio of execution cycles gained to the increase in code size) representing an if-condition or a loop, respectively, provided that the resultant code fits in the instruction buffer.

Abstract: Induction variable replacement (IVR) reduces operations in program loops. An IVR candidate is identified in a loop comprising linearly chained operations. The IVR candidate is derived from a basic induction variable (IV). A composite memory operation proceeding the IVR candidate is converted to unified form. Offset and increment information are separated from the composite memory operation. Constant values of the IVR candidate and a proceeding add operation are swapped. The composite memory operation is converted with an increment accommodating the preceding add operation. The add operation proceeding the composite memory operation is moved to the bottom of the series of operations. The basic IV is replaced with the IVR candidate, and the yield value of the loop is updated. The calculation for the basic IV is moved out of the loop, and the result value of the loop is adjusted to maintain the same behavior.

Abstract: A computer implemented method for generating modified loops for loops with a number of conditionals is provided. A processor set generates a conditional tree based on the number of conditionals in the loops. A value is determined by evaluating each conditional in the number of conditionals The processor set generates a multi-dimensional table based on values from the number of conditionals. The processor set determines an induction variable for the modified loops. The processor set slices the multi-dimensional table to generate a number of slices. The processor set generates a number of sequences by splitting values in each slice. The processor set generates a number of new conditionals based on the determined induction variable and at least values and strides in the number of sequences. The processor set generates the modified loops based on the number of new conditionals.

Abstract: Reducing live range of variables for register allocation of structured control-flow programs is provided. The method comprises defining an affine expression for each static single assignment (SSA) variable contained in an input program for a computer compiler. The affine expression of a SSA variable in the input program is derived by substitution of affine expressions of input operands involved in computation of the SSA variable. The method defines dependence edges between nodes representing the SSA variables in a dependence graph, wherein source and destination of dependence edges represent definition and use of the SSA variables. The method identifies one or more overlapping dependence edges with a same source among the dependence edges and eliminates the longer of the overlapping dependence edges according to the derived affine expressions.

Abstract: Described are techniques for reducing overhead controls. A loop tree is constructed from a program, such as a structured control flow program. Structured control flow refers to a programming concept where the flow of control to a block or region is based on single entry and single-exist methodology (SESE). A loop tree refers to a tree-like data structure that graphically represents loop(s) and/or an if-condition(s) in a program, such as a structured control flow program. A loop splitting operation or a loop unrolling operation may then be performed in connection with the node of the loop tree that is identified as having the highest benefit (ratio of execution cycles gained to the increase in code size) representing an if-condition or a loop, respectively, provided that the resultant code fits in the instruction buffer.

Abstract: A computer implemented method for merging loops. A number of processor units identifies loops in computer code. The loops are sequences of instructions that are repeated until conditions for the loops are reached. The number of processor units creates a tree comprising nodes that represent the loops and edges that represent relationships between nodes. The number of processor units utilizes the tree to identify a pair of candidate loops from sibling nodes. The number of processor units creates a new loop from the pair of candidate loops with an expanded iteration space based on iteration spaces for the pair of candidate loops in response to the pair of candidate loops being eligible for merging.

Abstract: Reducing live range of variables for register allocation of structured control-flow programs is provided. The method comprises defining an affine expression for each static single assignment (SSA) variable contained in an input program for a computer compiler. The affine expression of a SSA variable in the input program is derived by substitution of affine expressions of input operands involved in computation of the SSA variable. The method defines dependence edges between nodes representing the SSA variables in a dependence graph, wherein source and destination of dependence edges represent definition and use of the SSA variables. The method identifies one or more overlapping dependence edges with a same source among the dependence edges and eliminates the longer of the overlapping dependence edges according to the derived affine expressions.

Abstract: Induction variable replacement (IVR) reduces operations in program loops. An IVR candidate is identified in a loop comprising linearly chained operations. The IVR candidate is derived from a basic induction variable (IV). A composite memory operation proceeding the IVR candidate is converted to unified form. Offset and increment information are separated from the composite memory operation. Constant values of the IVR candidate and a proceeding add operation are swapped. The composite memory operation is converted with an increment accommodating the preceding add operation. The add operation proceeding the composite memory operation is moved to the bottom of the series of operations. The basic IV is replaced with the IVR candidate, and the yield value of the loop is updated. The calculation for the basic IV is moved out of the loop, and the result value of the loop is adjusted to maintain the same behavior.

Abstract: A computer implemented method for merging loops. A number of processor units identifies loops in computer code. The loops are sequences of instructions that are repeated until conditions for the loops are reached. The number of processor units creates a tree comprising nodes that represent the loops and edges that represent relationships between nodes. The number of processor units utilizes the tree to identify a pair of candidate loops from sibling nodes. The number of processor units creates a new loop from the pair of candidate loops with an expanded iteration space based on iteration spaces for the pair of candidate loops in response to the pair of candidate loops being eligible for merging.

Abstract: Disclosed approaches for generating vector codes include inputting tensor processing statements. Each statement specifies an output variable, an initial variable, and multiply-and-accumulate (MAC) operations, and each MAC operation references the output variable, elements of a first tensor, and one or more elements of a second tensor. The MAC operations are organized into groups, and the MAC operations in each group reference the same output variable and have overlapping references to elements of the first tensor. For each group of MAC operations, at least one instruction is generated to load elements of the first tensor into a first register and at least one instruction is generated to load one or more elements of the second tensor into a second register. For each group of MAC operations, instructions are generated to select for each MAC operation in the group for input to an array of MAC circuits, elements from the first register and one or more elements from the second register.