Patents by Inventor Prasanth K. Vallur

Prasanth K. Vallur has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10848135
    Abstract: A receiver circuit holds an output voltage at a first output voltage level using a first device of a first type coupled between a first node and a first power supply node, and a second device of a second type coupled between the first node and the first power supply node. The first device is selectively enabled using an input signal. The second device is selectively enabled using a feedback signal. The second device is substantially larger than the first device. The receiver circuit switches the output voltage from the first output voltage level to a second output voltage level responsive to an input voltage level transitioning across a first threshold voltage level from a first input voltage level to a second input voltage level.
    Type: Grant
    Filed: August 12, 2019
    Date of Patent: November 24, 2020
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Ashish Sahu, Girish Anathahally Singrigowda, Aniket Bharat Waghide, Prasanth K. Vallur
  • Patent number: 10247770
    Abstract: Various embodiments of a gate oxide breakdown detection technique detect gate oxide degradation due to stress on a per part basis without destroying functional circuits for an intended application. Stress on the gate oxide may be applied while nominal drain currents flow through a device, thereby stressing the device under conditions similar to actual operating conditions. The technique is relatively fast and does not require analog amplifiers or tuning of substantial amounts of other additional circuitry as compared to conventional gate oxide breakdown detection techniques.
    Type: Grant
    Filed: December 16, 2016
    Date of Patent: April 2, 2019
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Abhay Deshpande, Arun S. Iyer, Prasanth K. Vallur, Girish Anathahally Singrigowda, Stephen V. Kosonocky
  • Publication number: 20180172753
    Abstract: Various embodiments of a gate oxide breakdown detection technique detect gate oxide degradation due to stress on a per part basis without destroying functional circuits for an intended application. Stress on the gate oxide may be applied while nominal drain currents flow through a device, thereby stressing the device under conditions similar to actual operating conditions. The technique is relatively fast and does not require analog amplifiers or tuning of substantial amounts of other additional circuitry as compared to conventional gate oxide breakdown detection techniques.
    Type: Application
    Filed: December 16, 2016
    Publication date: June 21, 2018
    Inventors: Abhay Deshpande, Arun S. Iyer, Prasanth K. Vallur, Girish Anathahally Singrigowda, Stephen V. Kosonocky