Abstract: According to one general aspect, a method may include receiving a placed and routed circuit design, wherein the placed and routed circuit design includes a plurality of switch cells. The method may include performing a supply voltage drop analysis on the placed and routed circuit design. The method may also include creating a voltage drop map detailing a plurality of supply voltage drops across the placed and routed circuit design as a function of physical position. The method may further include determining one or more low voltage drop portions of the placed and routed circuit design that are associated with respective voltage drops below a predetermined threshold value. The method may include altering one or more switch cells included by the respective one or more low voltage portions.

Abstract: An embodiment includes a method, comprising: receiving a layout of an integrated circuit having a plurality of regions; determining a utilization for each of the regions; for each region, selecting from among a plurality of switch cell organizations for the region in response to the corresponding utilization; and for each region, modifying the layout to include switch cells for the region according to the selected switch cell organization.

Abstract: An embodiment includes a method, comprising: receiving a layout of an integrated circuit having a plurality of regions; determining a utilization for each of the regions; for each region, selecting from among a plurality of switch cell organizations for the region in response to the corresponding utilization; and for each region, modifying the layout to include switch cells for the region according to the selected switch cell organization.

Abstract: An embodiment includes a method, comprising: receiving a layout of an integrated circuit having a shape with a perimeter; offsetting at least a part of a segment of the perimeter of the shape from the perimeter to generate an offset segment; forming a route segment in response to the offset segment; generating at least a part of a route with the route segment; and routing a net in the layout of the integrated circuit using the part of the route. Nets for integrated circuits may be routed using such techniques.