Abstract: A method includes: receiving a representation of a mixed-signal integrated circuit design including an analog circuit portion and a digital circuit portion including a plurality of descriptions of a power supply, the descriptions including a power supply network description and a register transfer level (RTL) hardware description language (HDL) description; determining a mismatch between the power supply network description and the HDL description of the power supply; generating a value converter to convert a voltage value associated with the power supply between the power supply network description and the HDL description; and converting, by a processor, between the power supply network description and the HDL description during runtime using the value converter to synchronize the power supply network description and the HDL description of the power supply responsive to the mismatch.

Abstract: A system, apparatus, method, and article to process a chroma motion vector are described. The apparatus may include a video decoder. The video decoder includes a processor to receive a compressed video bitstream. The compressed video bitstream includes a stream of pictures. The stream of pictures includes a current slice and a current block within the slice. The processor pre-computes a chroma motion vector adjustment parameter for the current slice and determines a motion vector component for the current block within the current slice using the pre-computed chroma motion vector adjustment parameter.

Abstract: Apparatus, systems and methods for hardware accelerated compressed video bitstream escape code handling are disclosed including an apparatus comprising a bitstream parser (BSP) to parse a bitstream of compressed video data. The BSP includes circuitry to extract uncompressed run and level data from the bitstream when the BSP detects an escape code in the bitstream. Other implementations are disclosed.

Abstract: Apparatus, systems and methods for hardware accelerated compressed video bitstream escape code handling are disclosed including an apparatus comprising a bitstream parser (BSP) to parse a bitstream of compressed video data. The BSP includes circuitry to extract uncompressed run and level data from the bitstream when the BSP detects an escape code in the bitstream. Other implementations are disclosed.

Abstract: A system, apparatus, method, and article to process a flexible macroblock ordering and arbitrary slice ordering are described. The apparatus may include a video decoder. The video decoder includes a processor to store coding parameters of one or more neighboring macroblocks in a data buffer. The neighboring macroblocks are previously decoded macroblocks and are adjacent to a current macroblock. The processor is to store control parameters for each of the one or more neighboring macroblocks in the data buffer. The processor is to reconstruct coding parameters for the current macroblock using availability information associated with the neighboring macroblocks.

Abstract: Apparatus, systems and methods for hardware accelerated compressed video bitstream escape code handling are disclosed including an apparatus comprising a bitstream parser (BSP) to parse a bitstream of compressed video data. The BSP includes circuitry to extract uncompressed run and level data from the bitstream when the BSP detects an escape code in the bitstream. Other implementations are disclosed.

Abstract: A system, apparatus, method, and article to process a chroma motion vector are described. The apparatus may include a video decoder. The video decoder includes a processor to receive a compressed video bitstream. The compressed video bitstream includes a stream of pictures. The stream of pictures includes a current slice and a current block within the slice. The processor pre-computes a chroma motion vector adjustment parameter for the current slice and determines a motion vector component for the current block within the current slice using the pre-computed chroma motion vector adjustment parameter. Other embodiments are described and claimed.

Abstract: A system, apparatus, method, and article to process a chroma motion vector are described. The apparatus may include a video decoder. The video decoder includes a processor to receive a compressed video bitstream. The compressed video bitstream includes a stream of pictures. The stream of pictures includes a current slice and a current block within the slice. The processor pre-computes a chroma motion vector adjustment parameter for the current slice and determines a motion vector component for the current block within the current slice using the pre-computed chroma motion vector adjustment parameter.

Abstract: A system, apparatus, method, and article to process a flexible macroblock ordering and arbitrary slice ordering are described. The apparatus may include a video decoder. The video decoder includes a processor to store coding parameters of one or more neighboring macroblocks in a data buffer. The neighboring macroblocks are previously decoded macroblocks and are adjacent to a current macroblock. The processor is to store control parameters for each of the one or more neighboring macroblocks in the data buffer. The processor is to reconstruct coding parameters for the current macroblock using availability information associated with the neighboring macroblocks.

Abstract: A system, apparatus, method, and article to process a flexible macroblock ordering and arbitrary slice ordering are described. The apparatus may include a video decoder. The video decoder includes a processor to store coding parameters of one or more neighboring macroblocks in a data buffer. The neighboring macroblocks are previously decoded macroblocks and are adjacent to a current macroblock. The processor is to store control parameters for each of the one or more neighboring macroblocks in the data buffer. The processor is to reconstruct coding parameters for the current macroblock using availability information associated with the neighboring macroblocks.

Abstract: A system, apparatus, method, and article to process a flexible macroblock ordering and arbitrary slice ordering are described. The apparatus may include a video decoder. The video decoder includes a processor to store coding parameters of one or more neighboring macroblocks in a data buffer. The neighboring macroblocks are previously decoded macroblocks and are adjacent to a current macroblock. The processor is to store control parameters for each of the one or more neighboring macroblocks in the data buffer. The processor is to reconstruct coding parameters for the current macroblock using availability information associated with the neighboring macroblocks.

Abstract: A system, apparatus, method, and article to process a chroma motion vector are described. The apparatus may include a video decoder. The video decoder includes a processor to receive a compressed video bitstream. The compressed video bitstream includes a stream of pictures. The stream of pictures includes a current slice and a current block within the slice. The processor pre-computes a chroma motion vector adjustment parameter for the current slice and determines a motion vector component for the current block within the current slice using the pre-computed chroma motion vector adjustment parameter. Other embodiments are described and claimed.

Abstract: Apparatus, systems and methods for hardware accelerated compressed video bitstream escape code handling are disclosed including an apparatus comprising a bitstream parser (BSP) to parse a bitstream of compressed video data. The BSP includes circuitry to extract uncompressed run and level data from the bitstream when the BSP detects an escape code in the bitstream. Other implementations are disclosed.

Abstract: A method for modeling a mixed-language and mixed-signal (MLMS) design is disclosed. The method includes receiving an MLMS design comprising at least a digital driver, a digital receiver, and an analog block connected by an MLMS net in a hierarchical structure and identifying analog-digital boundaries of the MLMS design. For each analog-digital boundary, the method further includes a) selecting a connect module (CM) by using a predetermined discipline resolution procedure; b) determining input driving values of the CM; and c) connecting the digital driver, the digital receiver, and the analog block to the CM. The method repeats steps a), b), and c) on all analog-digital boundaries of the MLMS design.

Abstract: A method for connecting Verilog-AMS and VHDL-AMS components in a mixed-language mixed-signal design includes receiving a mixed-language mixed-signal design, where the mixed-language mixed-signal design comprises one or more VHDL-AMS and Verilog-AMS components, including a first VHDL-AMS component and a first Verilog-AMS component. The method further includes receiving a predetermined set of connection rules, resolving incompatibilities between the first VHDL-AMS component and the first Verilog-AMS component in accordance with the predetermined set of connection rules, and connecting the first VHDL-AMS component to the first Verilog-AMS component.

Abstract: An FPU pipeline is synchronized with a CPU pipeline. Synchronization is achieved by having stalls and freezes in any one pipeline cause stalls and freezes in the other pipeline as well. Exceptions are kept precise even for long floating point operations. Precise exceptions are achieved by having a first execution stage of the FPU pipeline generate a busy signal, when a first floating point instruction enters a first execution stage of the FPU pipeline. When a second floating point instruction is decoded by the FPU pipeline before the first floating point instruction has finished executing in the first stage of the FPU pipeline, then both pipelines are stalled.

Abstract: A method for modeling a mixed-language and mixed-signal (MLMS) design is disclosed. The method includes receiving an MLMS design comprising at least a digital driver, a digital receiver, and an analog block connected by an MLMS net in a hierarchical structure and identifying analog-digital boundaries of the MLMS design. For each analog-digital boundary, the method further includes a) selecting a connect module (CM) by using a predetermined discipline resolution procedure; b) determining input driving values of the CM; and c) connecting the digital driver, the digital receiver, and the analog block to the CM. The method repeats steps a), b), and c) on all analog-digital boundaries of the MLMS design.

Abstract: A method for connecting Verilog-AMS and VHDL-AMS components in a mixed-language mixed-signal design includes receiving a mixed-language mixed-signal design, where the mixed-language mixed-signal design comprises one or more VHDL-AMS and Verilog-AMS components, including a first VHDL-AMS component and a first Verilog-AMS component. The method further includes receiving a predetermined set of connection rules, resolving incompatibilities between the first VHDL-AMS component and the first Verilog-AMS component in accordance with the predetermined set of connection rules, and connecting the first VHDL-AMS component to the first Verilog-AMS component.

Abstract: A processor element, structured to execute a 32-bit fixed length instruction set architecture, is backward compatible with a 16-bit fixed length instruction set architecture by translating each of the 16-bit instructions into a sequence of one or more 32-bit instructions. Switching between 16-bit instruction execution and 32-bit instruction execution is accomplished by branch instructions that employ a least significant bit position of the address of the target of the branch to identify whether the target instruction is a 16-bit instruction or a 32-bit instruction.

Abstract: An FPU pipeline is synchronized with a CPU pipeline. Synchronization is achieved by having stalls and freezes in any one pipeline cause stalls and freezes in the other pipeline as well. Exceptions are kept precise even for long floating point operations. Precise exceptions are achieved by having a first execution stage of the FPU pipeline generate a busy signal, when a first floating point instruction enters a first execution stage of the FPU pipeline. When a second floating point instruction is decoded by the FPU pipeline before the first floating point instruction has finished executing in the first stage of the FPU pipeline, then both pipelines are stalled.