Patents by Inventor Prasenjit Chakraborty

Prasenjit Chakraborty has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250016237
    Abstract: An example method for communicating AI data from a sender device to a receiver device in a computing environment may include generating protocol instances of AI data; generating AI metadata description based on AI model information; sending a request comprising the AI metadata description to a receiver device for establishing a session; establishing a session by receiving a response from the receiver device based on the request; sending the AI data associated with the AI metadata description, to the receiver device based on the established session. The receiver device may receive the request and determine the compatibility of the metadata description, generate and send a response, followed by receiving the AI data associated with the AI metadata description.
    Type: Application
    Filed: September 24, 2024
    Publication date: January 9, 2025
    Inventors: Chandrashekhar S Byadgi, Kartik Anand, Praveen Naik S, Ramesh Babu Venkat Dabbiru, Siva Prasad Gundur, Prasenjit Chakraborty, Eric Ho Ching Yip
  • Patent number: 11956506
    Abstract: The disclosure relates to a method and system of selectively deploying an application for facilitating quality-of-experience (QoE) in terms of streaming multimedia content in a networking environment comprising a user-equipment (UE) and a networking node provided with a predictive analysis module. The method comprises: capturing parameters pertaining to UE from at least one of a version of the predictive analysis module with respect to the UE, a current processor occupancy within the UE, a power-level within the UE, network conditions pertaining to the access network etc. One or more of the captured parameters and the observed network conditions is analyzed. Based on analysis, inference is drawn for selecting between the predictive analysis model of the UE and of the networking node for thereby enabling a customized streaming of multimedia content at the UE.
    Type: Grant
    Filed: February 24, 2020
    Date of Patent: April 9, 2024
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sai Krishna Gairuboina, Prasenjit Chakraborty, Luckraj Shrawan Kumar, Karan Rakesh, Rishabh Mittar, Jongkyu Kim, Rajaram Hanumantacharya Naganur, Rajiv Chintala
  • Patent number: 11948276
    Abstract: A computer-implemented method includes obtaining, from a storage, a video to be enhanced, based on a selection of a user; determining corresponding sets of object scores for a plurality of objects identified in the video, respectively, based on a set of predetermined factors; identifying a primary object and one or more secondary objects in the video, among the plurality of objects, based on the corresponding sets of object scores; and applying at least one visual effect to the primary object and at least one secondary object, from the one or more secondary objects, in at least a portion of the video, for obtaining an enhanced video with the at least one visual effect applied at least to the portion of the video.
    Type: Grant
    Filed: January 15, 2021
    Date of Patent: April 2, 2024
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Shubham Rustagi, Sathish Cherukuri, Shashi Kumar Parwani, Mineni Niswanth Babu, Prasenjit Chakraborty
  • Patent number: 11412311
    Abstract: Embodiments herein provide methods and systems for saving data while streaming a video. The embodiments include streaming a first fragment of the video at a bit-rate based on network conditions. In an embodiment, the scene content complexity of the first fragment can be analyzed while streaming the first fragment. Based on the screen complexity, the second fragment can be streamed at a bit-rate based on the network conditions and the analyzed screen complexity. In another embodiment, a second fragment can be received at a minimum possible resolution and, thereafter, the scene content complexity of the second fragment can be analyzed while streaming the first fragment. Based on the screen complexity of the second fragment, it can be streamed at a bit-rate based on the network conditions and the analyzed screen complexity. There may be no perceptible difference in streamed quality of the first fragment and the second fragment.
    Type: Grant
    Filed: May 8, 2018
    Date of Patent: August 9, 2022
    Inventors: Prasenjit Chakraborty, Om Prakash, Sachin Dev, Shweta Aggarwal
  • Patent number: 9552205
    Abstract: A processor including a decode unit to receive a vector indexed load plus arithmetic and/or logical (A/L) operation plus store instruction. The instruction is to indicate a source packed memory indices operand that is to have a plurality of packed memory indices. The instruction is also to indicate a source packed data operand that is to have a plurality of packed data elements. The processor also includes an execution unit coupled with the decode unit. The execution unit, in response to the instruction, is to load a plurality of data elements from memory locations corresponding to the plurality of packed memory indices, perform A/L operations on the plurality of packed data elements of the source packed data operand and the loaded plurality of data elements, and store a plurality of result data elements in the memory locations corresponding to the plurality of packed memory indices.
    Type: Grant
    Filed: September 27, 2013
    Date of Patent: January 24, 2017
    Assignee: Intel Corporation
    Inventors: Igor Ermolaev, Bret L. Toll, Robert Valentine, Jesus Corbal San Adrian, Gautam B. Doshi, Rama Kishan V. Malladi, Prasenjit Chakraborty
  • Publication number: 20150095623
    Abstract: A processor including a decode unit to receive a vector indexed load plus arithmetic and/or logical (A/L) operation plus store instruction. The instruction is to indicate a source packed memory indices operand that is to have a plurality of packed memory indices. The instruction is also to indicate a source packed data operand that is to have a plurality of packed data elements. The processor also includes an execution unit coupled with the decode unit. The execution unit, in response to the instruction, is to load a plurality of data elements from memory locations corresponding to the plurality of packed memory indices, perform A/L operations on the plurality of packed data elements of the source packed data operand and the loaded plurality of data elements, and store a plurality of result data elements in the memory locations corresponding to the plurality of packed memory indices.
    Type: Application
    Filed: September 27, 2013
    Publication date: April 2, 2015
    Inventors: Igor Ermolaev, Bret L. Toll, Robert Valentine, Jesus Corbal San Adrian, Gautam B. Doshi, Rama Kishan V. Malladi, Prasenjit Chakraborty
  • Patent number: 8615636
    Abstract: This invention is a method and system for replacing an entry in a cache memory (replacement policy). The cache is divided into a high-priority class and a low-priority class. Upon a request for information such as data, an instruction, or an address translation, the processor searches the cache. If there is a cache miss, the processor locates the information elsewhere, typically in memory. The found information replaces an existing entry in the cache. The entry selected for replacement (eviction) is chosen from within the low-priority class using a FIFO algorithm. Upon a cache hit, the processor performs a read, write, or execute using or upon the information. If the performed instruction was a “write”, the information is placed into the high-priority class. If the high-priority class is full, an entry within the high-priority class is selected for removal based on a FIFO algorithm, and re-classified into the low-priority class.
    Type: Grant
    Filed: March 3, 2011
    Date of Patent: December 24, 2013
    Assignee: International Business Machines Corporation
    Inventors: Jason Frederick Cantin, Prasenjit Chakraborty
  • Publication number: 20120226871
    Abstract: This invention is a method and system for replacing an entry in a cache memory (replacement policy). The cache is divided into a high-priority class and a low-priority class. Upon a request for information such as data, an instruction, or an address translation, the processor searches the cache. If there is a cache miss, the processor locates the information elsewhere, typically in memory. The found information replaces an existing entry in the cache. The entry selected for replacement (eviction) is chosen from within the low-priority class using a FIFO algorithm. Upon a cache hit, the processor performs a read, write, or execute using or upon the information. If the performed instruction was a “write”, the information is placed into the high-priority class. If the high-priority class is full, an entry within the high-priority class is selected for removal based on a FIFO algorithm, and re-classified into the low-priority class.
    Type: Application
    Filed: March 3, 2011
    Publication date: September 6, 2012
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Jason Frederick Cantin, Prasenjit Chakraborty