Patents by Inventor Prashant A. Kanhere

Prashant A. Kanhere has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5287458
    Abstract: An asynchronous communications element which incorporates user-selectable FIFOs both as transmitter and receiver buffers to reduce CPU interrupt overhead. The asynchronous communications element includes a receiver shift register which receives serial data transfers from a communication station, a receiver FIFO which receives parallel data transfers from the receiver shift register for transfer to the CPU, a transmitter FIFO which receives parallel data transfers from the CPU, and a transmitter shift register which receives parallel data transfers from the transmitter FIFO for serial transfer to the communications station. A transmitter time delay eliminates multiple interrupts for a transmitter FIFO "empty" condition that has already been indicated to the CPU. Programmable interrupt levels on the receiver FIFO, together with a receiver FIFO that continues to fill beyond the programmed interrupt level, allow adjustments for variable CPU latency times.
    Type: Grant
    Filed: March 26, 1993
    Date of Patent: February 15, 1994
    Assignee: National Semiconductor Corporation
    Inventors: Martin S. Michael, Prashant A. Kanhere, Richard P. Burnley, Franco Iacobelli, Ta-Wei Chien
  • Patent number: 5241660
    Abstract: An asynchronous communications element which incorporates user-selectable FIFOs both as transmitter and receiver buffers to reduce CPU interrupt overhead. The asynchronous communications element includes a receiver shift register which receives serial data transfers from a communication station, a receiver FIFO which receives parallel data transfers from the receiver shift register for transfer to the CPU, a transmitter FIFO which receives parallel data transfers from the CPU, and a transmitter shift register which receives parallel data transfers from the transmitter FIFO for serial transfer to the communications station. A transmitter time delay eliminates multiple interrupts for a transmitter FIFO "empty" condition that has already been indicated to the CPU. Programmable interrupt levels on the receiver FIFO, together with a receiver FIFO that continues to fill beyond the programmed interrupt level, allow adjustments for variable CPU latency times.
    Type: Grant
    Filed: May 17, 1991
    Date of Patent: August 31, 1993
    Assignee: National Semiconductor Corporation
    Inventors: Martin S. Michael, Prashant A. Kanhere, Richard P. Burnley, Franco Iacobelli, Ta-Wei Chien
  • Patent number: 4823312
    Abstract: An asynchronous communications element which incorporates user-selectable FIFOs both as transmitter and receiver buffers to reduce CPU interrupt overhead.The asynchronous communications element includes a receiver shift register which receives serial data transfers from a communications station, a receiver FIFO which receives parallel data transfers from the receiver shift register for transfer to the CPU, a transmitter FIFO which receives parallel data transfers from the CPU, and a transmitter shift register which receives parallel data transfers from the transmitter FIFO for serial transfer to the communications station. A transmitter time delay eliminates multiple interrupts for a transmitter FIFO "empty" condition that has already been indicated to the CPU. Programmable interrupt levels on the receiver FIFO, together with a receiver FIFO that continues to fill beyond the programmed interrupt level, allow adjustments for variable CPU latency times.
    Type: Grant
    Filed: October 30, 1986
    Date of Patent: April 18, 1989
    Assignee: National Semiconductor Corp.
    Inventors: Martin S. Michael, Prashant A. Kanhere, Richard P. Burnley, Franco Iacobelli, Ta-Wei Chien