Abstract: A method, performed by a first node. The method is for handling anomalous values. The first node determines whether an anomalous value is present in a first distribution of values (M) over a first time period. The values are indicative of a performance of a communications system. The first distribution has a first variability per time point. The determining including defining a subset of second time periods within the first time period. The second time periods are equally spaced in time. The determining including determining a second variability of a second distribution (S) of a subset of the values corresponding to the subset of second periods. The determining further including detecting the presence of the anomalous value according to a threshold, based on a variation along time of the second variability. The first node also provides a result of the determination.

Abstract: An active tamper detection circuit with bypass detection is provided. A bypass detection circuit is coupled to an active mesh loop. The bypass detector includes a voltage comparator with a variable hysteresis control circuit and a calibration engine. The bypass detector detects a change in impedance in the mesh when an attacker attempts to bypass the active loop using a wire. As part of a boot-up sequence, the calibration engine runs a hysteresis sweep on the voltage comparator and stores a hysteresis sweep boot-up signature. When bypass protection is enabled, the bypass detector runs a hysteresis sweep of the voltage comparator periodically at a predetermined interval. Each sweep generates a generated signature that is compared to the stored boot-up signature. Any signature mismatch will be signaled as an impedance mismatch, or tamper. The hysteresis step size is also programmable. The calibration engine can make small changes to the boot-up signature to allow for small voltage variations.

Abstract: An active tamper detection circuit with bypass detection is provided. A bypass detection circuit is coupled to an active mesh loop. The bypass detector includes a voltage comparator with a variable hysteresis control circuit and a calibration engine. The bypass detector detects a change in impedance in the mesh when an attacker attempts to bypass the active loop using a wire. As part of a boot-up sequence, the calibration engine runs a hysteresis sweep on the voltage comparator and stores a hysteresis sweep boot-up signature. When bypass protection is enabled, the bypass detector runs a hysteresis sweep of the voltage comparator periodically at a predetermined interval. Each sweep generates a generated signature that is compared to the stored boot-up signature. Any signature mismatch will be signaled as an impedance mismatch, or tamper. The hysteresis step size is also programmable. The calibration engine can make small changes to the boot-up signature to allow for small voltage variations.

Abstract: A processing system includes a processor and a temperature security module coupled to provide a temperature tamper signal to the processor. The temperature security module includes a shelf mode trim value, an operating mode trim value, and a programmable temperature trim value. One of the programmable temperature trim value, the shelf mode trim value, and the operating mode trim value, is used based on a deployment mode of the processing system to set a temperature monitor trim value.

Abstract: A processing system includes a processor and a temperature security module coupled to provide a temperature tamper signal to the processor. The temperature security module includes a shelf mode trim value, an operating mode trim value, and a programmable temperature trim value. One of the programmable temperature trim value, the shelf mode trim value, and the operating mode trim value, is used based on a deployment mode of the processing system to set a temperature monitor trim value.

Abstract: A tamper detector has tamper detection logic connected to tamper detection ports through a tamper detection interface. A real-time clock (RTC) provides a clock signal and has a battery. A processor is powered by an external power supply in a powered operational mode and has a power-off mode. In a wake-up configuration, a wake-up signal on a specific I/O port awakens the external power supply from the power-off mode to supply power to the RTC and the tamper detection interface when power from the battery is unavailable. The tamper detection ports continue to function despite removal or discharge of the battery without ESD concerns. The specific I/O port optionally may be configured for passive tamper detection.

Abstract: A tamper detector has tamper detection logic connected to tamper detection ports through a tamper detection interface. A real-time clock (RTC) provides a clock signal and has a battery. A processor is powered by an external power supply in a powered operational mode and has a power-off mode. In a wake-up configuration, a wake-up signal on a specific I/O port awakens the external power supply from the power-off mode to supply power to the RTC and the tamper detection interface when power from the battery is unavailable. The tamper detection ports continue to function despite removal or discharge of the battery without ESD concerns. The specific I/O port optionally may be configured for passive tamper detection.

Abstract: A microcontroller includes a clock generator having an internal reference clock, a system mode controller establishing an operating mode, a flash memory having an internal clock and a non-volatile option register, and a boot mode selection logic circuit coupled to the system mode controller and the flash memory. The logic circuit outputs a boot mode selection signal instructing the microcontroller to boot in a very low power run (VLPR) mode or a RUN mode. The system mode controller enters the VLPR or RUN mode in response. The flash memory bypasses and disables its internal clock prior to calibration of the flash memory in the VLPR mode and prior to initialization of the flash memory in the RUN mode. The flash memory subsequently uses an external clock signal based on the output of the internal reference clock.

Abstract: A system for securing a real-time clock (RTC) of an electronic device includes a RTC counter that counts clock pulses of a RTC signal generated by a crystal oscillator, and a reference-time register that periodically stores a reference time value generated by a network-clock generator. A hash-value generator uses a predefined hash algorithm to generate first and second hash values based on the reference time value and the count of the RTC counter, respectively, at predetermined time intervals. A comparator compares the first and second hash values and generates a trigger signal when there is a mismatch.

Abstract: A system for performing diagnostic checks on a data message transmitted from a sensor and received by a receiver includes a receiver clock tick counter, a prescaler counter, a calibration pulse detector, a nibble counter, and a calculator. The system receives first and second data messages transmitted from the sensor. Pulse widths of first and second calibration pulses of the first and second data messages, respectively, and lengths of the first and second data messages are measured using the receiver clock tick, prescaler, and nibble counters based on a compensated receiver clock signal. Thereafter, the pulse widths of the first and second calibration pulses and the lengths of the first and second data messages are compared using the calculator to perform the diagnostic checks.

Abstract: A microcontroller includes a clock generator having an internal reference clock, a system mode controller establishing an operating mode, a flash memory having an internal clock and a non-volatile option register, and a boot mode selection logic circuit coupled to the system mode controller and the flash memory. The logic circuit outputs a boot mode selection signal instructing the microcontroller to boot in a very low power run (VLPR) mode or a RUN mode. The system mode controller enters the VLPR or RUN mode in response. The flash memory bypasses and disables its internal clock prior to calibration of the flash memory in the VLPR mode and prior to initialization of the flash memory in the RUN mode. The flash memory subsequently uses an external clock signal based on the output of the internal reference clock.

Abstract: A system for generating a tamper detection signal indicating tampering with one or more circuits of an integrated circuit (IC) includes a tamper detection module, and wire-pairs connected to the tamper detection module and arranged in a winding configuration to form a wire-mesh. The wire-mesh is placed a predefined distance from the circuits. The tamper detection module generates and provides serial bit-streams to the wire-pairs for detecting a breach in the wire-mesh by an external probe.

Abstract: A system for generating a tamper detection signal indicating tampering with one or more circuits of an integrated circuit (IC) includes a tamper detection module, and wire-pairs connected to the tamper detection module and arranged in a winding configuration to form a wire-mesh. The wire-mesh is placed a predefined distance from the circuits. The tamper detection module generates and provides serial bit-streams to the wire-pairs for detecting a breach in the wire-mesh by an external probe.

Abstract: A memory error management system connected to memory channels for managing errors detected in corresponding memory devices includes a reporting table including a list of historically reported errors, a binary value representing the current error status of the memory channels, a uniqueness check module for checking whether a historically reported error is reappearing as a current error, an error mask register for generating a masked binary value representing unique current errors in the memory channels, and a channel arbitration module for decoding the channel identifiers of corrupted memory channels from the masked binary value and storing the decoded channel identifiers into the reporting table.

Abstract: A memory error management system connected to memory channels for managing errors detected in corresponding memory devices includes a reporting table including a list of historically reported errors, a binary value representing the current error status of the memory channels, a uniqueness check module for checking whether a historically reported error is reappearing as a current error, an error mask register for generating a masked binary value representing unique current errors in the memory channels, and a channel arbitration module for decoding the channel identifiers of corrupted memory channels from the masked binary value and storing the decoded channel identifiers into the reporting table.

Abstract: A system for performing diagnostic checks on a data message transmitted from a sensor and received by a receiver includes a receiver clock tick counter, a prescaler counter, a calibration pulse detector, a nibble counter, and a calculator. The system receives first and second data messages transmitted from the sensor. Pulse widths of first and second calibration pulses of the first and second data messages, respectively, and lengths of the first and second data messages are measured using the receiver clock tick, prescaler, and nibble counters based on a compensated receiver clock signal. Thereafter, the pulse widths of the first and second calibration pulses and the lengths of the first and second data messages are compared using the calculator to perform the diagnostic checks.

Abstract: A tamper detector has input and output pins for connection to ends of a tamper detection circuit, and a corresponding set of linear feedback shift registers (LFSRs) timed by clock signals for generating pseudo-random coded detection signals as a function of seed values and of a generator polynomial defined by feedback taps. A comparator compares signals received from the detection circuit with the coded detection signals. A multiplexer provides the coded detection signal selectively from the LFSRs to the output pin and the comparator. A controller varies the seed values for different cycles of values of the pseudo-random coded detection signals. The controller also controls the generator polynomial and a frequency of the clock signals for different cycles of values of the pseudo-random coded detection signals.

Abstract: A system for performing diagnostic checks on a data message transmitted from a sensor and received by a receiver includes a receiver clock tick counter, a prescaler counter, a calibration pulse detector, a nibble counter, and a calculator. The system receives first and second data messages transmitted from the sensor. Pulse widths of first and second calibration pulses of the first and second data messages, respectively, and lengths of the first and second data messages are measured using the receiver clock tick, prescaler, and nibble counters based on a compensated receiver clock signal. Thereafter, the pulse widths of the first and second calibration pulses and the lengths of the first and second data messages are compared using the calculator to perform the diagnostic checks.

Abstract: A system for compensating for variations in the frequency of an input clock signal having a first frequency includes a coarse counter that receives the input clock signal, counts a predetermined number of clock pulses of the input clock signal, and generates a coarse compensated clock signal having a second frequency. A first compensation module adjusts a clock pulse of the input clock signal based on a coarse compensation value. A residual period adjustment module accumulates a fine compensation value for each clock pulse of the coarse compensated clock signal. A fine counter operates at a third frequency of a fine clock signal, receives an adjusted delay value based on the accumulated fine compensation value, counts a number of fine clock pulses in each clock pulse of the coarse compensated clock signal, and generates a fine compensated clock signal having the second frequency.

Abstract: A system for performing diagnostic checks on a data message transmitted from a sensor and received by a receiver includes a receiver clock tick counter, a prescaler counter, a calibration pulse detector, a nibble counter, and a calculator. The system receives first and second data messages transmitted from the sensor. Pulse widths of first and second calibration pulses of the first and second data messages, respectively, and lengths of the first and second data messages are measured using the receiver clock tick, prescaler, and nibble counters based on a compensated receiver clock signal. Thereafter, the pulse widths of the first and second calibration pulses and the lengths of the first and second data messages are compared using the calculator to perform the diagnostic checks.