Patents by Inventor Prashant Chandra

Prashant Chandra has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12132800
    Abstract: A communication technology that provides for handling of failed packet transmissions to reduce retransmission attempts and uses resynchronization to prevent tearing down of connections. Thereby, providing for more resilient connections. In an implementation, an initiator entity may determine that a negative acknowledgment indicates that an operation for a particular packet is completed in error by a target entity, and transmit to the target entity a resynchronization packet without tearing down the connection.
    Type: Grant
    Filed: September 13, 2023
    Date of Patent: October 29, 2024
    Assignee: Google LLC
    Inventors: Weihuang Wang, Prashant Chandra, Srinivas Vaduvatha
  • Patent number: 12132802
    Abstract: An application specific integrated circuit (ASIC) is provided for reliable transport of packets. The network interface card may include a reliable transport accelerator (RTA). The RTA may include a cache lookup database. The RTA may be configured to determine, from a received data packet, a connection identifier and query the cache lookup database for a cache entry corresponding to a connection context having the connection identifier. In response to the query, the RTA may receive a cache hit or a cache miss.
    Type: Grant
    Filed: December 16, 2021
    Date of Patent: October 29, 2024
    Assignee: Google LLC
    Inventors: Weihuang Wang, Srinivas Vaduvatha, Xiaoming Wang, Gurushankar Rajamani, Abhishek Agarwal, Jiazhen Zheng, Prashant Chandra
  • Publication number: 20240333660
    Abstract: A method of communication in a vehicle network is provided. An example method includes transmitting a network allocation map in a TDMA cycle, indicating reservation of time slots in the TDMA cycle. The method further includes transmitting a synchronization signal in the TDMA cycle, to synchronize the timing of nodes in the vehicle network. Each of the reserved time slots is identified by at least a network ID of a transmitting node in the vehicle network, and a slot type comprising one of a low latency traffic slot, and a bulk traffic slot. Further, the low latency traffic slots are repeated in the TDMA cycle at least as frequently as a guaranteed QoS latency parameter. Further, the bulk traffic slots are at least as long as a guaranteed QoS throughput parameter.
    Type: Application
    Filed: June 10, 2024
    Publication date: October 3, 2024
    Inventors: Adnan Esmail, Prashant Joshi, Sundar Balasubramaniam, Brijesh Tripathi, Gaurav Chandra
  • Patent number: 12040988
    Abstract: A communication protocol system is provided for reliable transport of packets. A content addressable memory hardware architecture including an acknowledgment coalescing module in communication with a content addressable memory (CAM). The acknowledgment coalescing module coalesces multiple acknowledgement packets as a single acknowledgement packet to reduce the overall numbers of the packet transmission in the communication protocol system. In addition, the acknowledgment coalescing module may also provide a piggyback mechanism to carry acknowledge information in a regular data packet. Thus, the need to generate a new acknowledgement packet may be eliminated. Accordingly, the network congestion and latency may be reduced, and the communication and transmission efficiency are enhanced.
    Type: Grant
    Filed: December 16, 2021
    Date of Patent: July 16, 2024
    Assignee: Google LLC
    Inventors: Srinivas Vaduvatha, Weihuang Wang, Jiazhen Zheng, Prashant Chandra
  • Patent number: 11979330
    Abstract: A system includes a first processor configured to analyze packets received over a communication protocol system and determine one or more congestion indicators from the analysis of the data packets, the one or more congestion indicators being indicative of network congestion for data packets transmitted over a reliable transport protocol layer of the communication protocol system. The system also includes a rate update engine separate from the packet datapath and configured to operate a second processor to receive the determined one or more congestion indicators, determine one or more congestion control parameters for controlling transmission of data packets based on the received one or more congestion indicators, and output a congestion control result based on the determined one or more congestion control parameters.
    Type: Grant
    Filed: June 22, 2020
    Date of Patent: May 7, 2024
    Assignee: Google LLC
    Inventors: Xiaoming Wang, Prashant Chandra, Neelesh Bansod, Nandita Dukkipati, Hassan Wassel, Gautam Kumar, Weihuang Wang, Michael Marty, Nicholas McDonald
  • Patent number: 11960413
    Abstract: A flow table management system can include a hardware memory module communicatively coupled to a network interface card. The hardware memory module is configured to store a flow table including a plurality of network flow entries. The network interface card further includes a flow table age cache configured to store a set of recently active network flows and a flow table management module configured to manage a duration for which respective network flow entries in the flow table stored in the hardware memory module remain in the flow table using the flow table age cache. In some implementations, age information about each respective flow in the flow table is stored in the hardware memory module in an age state table that is separate from the flow table.
    Type: Grant
    Filed: February 27, 2023
    Date of Patent: April 16, 2024
    Assignee: Google LLC
    Inventors: Weihuang Wang, Prashant Chandra
  • Publication number: 20240064215
    Abstract: Compressing connection state information for a network connection including receiving an input bitmap having a sequence of bits describing transmit states and receive states; partitioning the input bitmap into a plurality of equal size blocks; partitioning each of the blocks into a plurality of equal sized sectors; generating a block valid sequence indicating the blocks having at least one bit set; generating, for each block having at least one bit set, a sector information sequence, the sector information sequence indicating, for the corresponding block, the sectors that have at least one bit set and an encoding type for each sector; and generating one or more symbols by encoding each sector that has at least one bit set.
    Type: Application
    Filed: May 22, 2023
    Publication date: February 22, 2024
    Inventors: Srinivas Vaduvatha, Weiwei Jiang, Prashant Chandra, Opeoluwa Oladipo, Jiazhen Zheng, Hugh McEvoy Walsh, Weihuang Wang, Abhishek Agarwal
  • Publication number: 20230418775
    Abstract: The present disclosure provides for a converged compute platform architecture, including a first infrastructure processing unit (IPU)-only configuration and a second configuration wherein the IPU is coupled to a central processing unit, such as an x86 processor. Connectivity between the two configurations may be accomplished with a PCIe switch, or the two configurations may communicate through remote direct memory access (RDMA) techniques. Both configurations may use ML acceleration through a single converged architecture.
    Type: Application
    Filed: June 22, 2023
    Publication date: December 28, 2023
    Inventors: Santanu Dasgupta, Bok Knun Randolph Chung, Ankur Jain, Prashant Chandra, Bor Chan, Durgaprasad V. Ayyadevara, Ian Kenneth Coolidge, Muzammil Mueen Butt
  • Publication number: 20230421657
    Abstract: A communication protocol system is provided for reliable transport of packets. In this regard, an initiator entity may determine that outgoing data is to be transmitted to a target entity. The initiator entity may transmit, to the target entity, a solicited push request requesting the outgoing data to be placed at the target entity. In response to the solicited push request, the initiator entity may receive a push grant from the target entity. In response to the push grant, the initiator entity may transmit to the target entity the outgoing data to be placed at the target entity.
    Type: Application
    Filed: September 13, 2023
    Publication date: December 28, 2023
    Inventors: Weihuang Wang, Prashant Chandra, Srinivas Vaduvatha
  • Patent number: 11831550
    Abstract: A network interface card with traffic shaping capabilities and methods of network traffic shaping with a network interface card are provided. The network interface card and method can shape traffic originating from one or more applications executing on a host network device. The applications can execute in a virtual machine or containerized computing environment. The network interface card and method can perform or include several traffic shaping mechanisms including, for example and without limitation, a delayed completion mechanism, a time-indexed data structure, a packet builder, and a memory manager.
    Type: Grant
    Filed: December 28, 2021
    Date of Patent: November 28, 2023
    Assignee: Google LLC
    Inventors: Prashant Chandra, Nandita Dukkipati, Vytautas Valancius
  • Publication number: 20230379247
    Abstract: Systems and methods of offloading multicast virtual network packet processing to a network interface card are provided. In an example implementation, a network interface card can route packets in a virtual network. The network interface card can be configured to receive a data packet having a multicast header for transmission to a plurality of destination virtual machines. The network interface card can retrieve a list of next hop destinations for the data packet. The network interface card can replicate the packet for each next hop destination. The network interface card can encapsulate each replicated packet with a unicast header that includes a next hop destination virtual IP address indicating the next hop destination and a source virtual IP address, and transmit the encapsulated packets.
    Type: Application
    Filed: August 3, 2023
    Publication date: November 23, 2023
    Inventors: Prashant Chandra, Balakrishna Raghunath, Uday Ramakrishna Naik, Michael Dalton
  • Publication number: 20230362098
    Abstract: A system includes a first processor configured to analyze packets received over a communication protocol system and determine one or more congestion indicators from the analysis of the data packets, the one or more congestion indicators being indicative of network congestion for data packets transmitted over a reliable transport protocol layer of the communication protocol system. The system also includes a rate update engine separate from the packet datapath and configured to operate a second processor to receive the determined one or more congestion indicators, determine one or more congestion control parameters for controlling transmission of data packets based on the received one or more congestion indicators, and output a congestion control result based on the determined one or more congestion control parameters.
    Type: Application
    Filed: July 17, 2023
    Publication date: November 9, 2023
    Inventors: Xiaoming Wang, Prashant Chandra, Neelesh Bansod, Nandita Dukkipati, Hassan Wassel, Gautam Kumar, Weihuang Wang, Michael Marty, Nicholas McDonald
  • Patent number: 11799577
    Abstract: A system is provided for synchronizing clocks. The system includes a plurality of devices in a network, each device having a local clock. The system is configured to synchronize the local clocks according to a primary spanning tree, where the primary spanning tree has a plurality of nodes connected through a plurality of primary links, each node of the plurality of nodes representing a respective device of the plurality of devices. The system is also configured to compute a backup spanning tree before a failure is detected in the primary spanning tree, wherein the backup spanning tree includes one or more backup links that are different from the primary links. As such, upon detection of a failure in the primary spanning tree, the system reconfigures the plurality of devices such that clock synchronization is performed according to the backup spanning tree.
    Type: Grant
    Filed: August 19, 2022
    Date of Patent: October 24, 2023
    Assignee: Google LLC
    Inventors: Yuliang Li, Gautam Kumar, Nandita Dukkipati, Hassan Wassel, Prashant Chandra, Amin Vahdat
  • Patent number: 11711311
    Abstract: A system includes a first processor configured to analyze packets received over a communication protocol system and determine one or more congestion indicators from the analysis of the data packets, the one or more congestion indicators being indicative of network congestion for data packets transmitted over a reliable transport protocol layer of the communication protocol system. The system also includes a rate update engine separate from the packet datapath and configured to operate a second processor to receive the determined one or more congestion indicators, determine one or more congestion control parameters for controlling transmission of data packets based on the received one or more congestion indicators, and output a congestion control result based on the determined one or more congestion control parameters.
    Type: Grant
    Filed: June 22, 2020
    Date of Patent: July 25, 2023
    Assignee: Google LLC
    Inventors: Xiaoming Wang, Prashant Chandra, Neelesh Bansod, Nandita Dukkipati, Hassan Wassel, Gautam Kumar, Weihuang Wang, Michael Marty, Nicholas McDonald
  • Patent number: 11698868
    Abstract: Systems and methods of tracking page state changes are provided. An input/output is communicatively coupled to a host having a memory. The I/O device receives a command from the host to monitor page state changes in a region of the memory allocated to a process. The I/O device, bypassing a CPU of the host, modifies data stored in the region based on a request, for example, received from a client device via a computer network. The I/O device records the modification to a bitmap by setting a bit in the bitmap that corresponds to a location of the data in the memory. The I/O device transfers contents of the bitmap to the CPU, wherein the CPU completes the live migration by copying sections of the first region indicated by the bitmap to a second region of memory. In some implementations, the process can be a virtual machine, a user space application, or a container.
    Type: Grant
    Filed: September 21, 2021
    Date of Patent: July 11, 2023
    Assignee: Google LLC
    Inventors: Shrijeet Mukherjee, Prashant Chandra, Joseph Raymond Michael Zbiciak, Horacio Andres Lagar Cavilla, David Alan Dillow
  • Publication number: 20230205708
    Abstract: A flow table management system can include a hardware memory module communicatively coupled to a network interface card. The hardware memory module is configured to store a flow table including a plurality of network flow entries. The network interface card further includes a flow table age cache configured to store a set of recently active network flows and a flow table management module configured to manage a duration for which respective network flow entries in the flow table stored in the hardware memory module remain in the flow table using the flow table age cache. In some implementations, age information about each respective flow in the flow table is stored in the hardware memory module in an age state table that is separate from the flow table.
    Type: Application
    Filed: February 27, 2023
    Publication date: June 29, 2023
    Inventors: Weihuang Wang, Prashant Chandra
  • Publication number: 20230173090
    Abstract: The present disclosure provides conjugates and systems for modulating the activity of a ligand-binding polypeptide such as a D1 dopamine receptor. The present disclosure provides methods of modulating the activity of a D1 dopamine receptor. The present disclosure provides methods of treating Parkinson’s disease in an individual.
    Type: Application
    Filed: June 29, 2021
    Publication date: June 8, 2023
    Inventors: Ehud Y. Isacoff, Prashant Chandra Donthamsetti
  • Patent number: 11620237
    Abstract: A flow table management system can include a hardware memory module communicatively coupled to a network interface card. The hardware memory module is configured to store a flow table including a plurality of network flow entries. The network interface card further includes a flow table age cache configured to store a set of recently active network flows and a flow table management module configured to manage a duration for which respective network flow entries in the flow table stored in the hardware memory module remain in the flow table using the flow table age cache. In some implementations, age information about each respective flow in the flow table is stored in the hardware memory module in an age state table that is separate from the flow table.
    Type: Grant
    Filed: October 25, 2021
    Date of Patent: April 4, 2023
    Assignee: Google LLC
    Inventors: Weihuang Wang, Prashant Chandra
  • Publication number: 20230062889
    Abstract: An application specific integrated circuit (ASIC) is provided for reliable transport of packets. The network interface card may include a reliable transport accelerator (RTA). The RTA may include a cache lookup database. The RTA may be configured to determine, from a received data packet, a connection identifier and query the cache lookup database for a cache entry corresponding to a connection context having the connection identifier. In response to the query, the RTA may receive a cache hit or a cache miss.
    Type: Application
    Filed: December 16, 2021
    Publication date: March 2, 2023
    Inventors: Weihuang Wang, Srinivas Vaduvatha, Xiaoming Wang, Gurushankar Rajamani, Abhishek Agarwal, Jiazhen Zheng, Prashant Chandra
  • Publication number: 20220393783
    Abstract: A system is provided for synchronizing clocks. The system includes a plurality of devices in a network, each device having a local clock. The system is configured to synchronize the local clocks according to a primary spanning tree, where the primary spanning tree has a plurality of nodes connected through a plurality of primary links, each node of the plurality of nodes representing a respective device of the plurality of devices. The system is also configured to compute a backup spanning tree before a failure is detected in the primary spanning tree, wherein the backup spanning tree includes one or more backup links that are different from the primary links. As such, upon detection of a failure in the primary spanning tree, the system reconfigures the plurality of devices such that clock synchronization is performed according to the backup spanning tree.
    Type: Application
    Filed: August 19, 2022
    Publication date: December 8, 2022
    Inventors: Yuliang Li, Gautam Kumar, Nandita Dukkipati, Hassan Wassel, Prashant Chandra, Amin Vahdat